三維多位元垂直電阻式記憶體之研究

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姓名

陳煥勳(Huan-Xun Chen) 查詢紙本館藏

畢業系所

化學工程與材料工程學系

論文名稱

三維多位元垂直電阻式記憶體之研究
(The Research of Three-Dimensional Multi-bit Vertical Resistive-Switching Random Access Memory)

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摘要(中)

電阻式記憶體(RRAM)有著結構簡單的特性，因此具有發展高密度記憶體的潛力，本研究的研究重點即在於利用垂直結構來提高元件的密度，且雙層垂直電阻式記憶體更能有效發揮出高密度的特點。
實驗分為兩部分，第一部分是討論二氧化鉿薄膜製作之雙層垂直電阻式記憶體在不同二氧化鉿厚度及操作面積的情況下其電性的比較。第二部分是討論不同厚度之非晶矽薄膜於垂直電阻式記憶體的電性比較，選擇二氧化鉿以及非晶矽薄膜做為介電層的原因為這兩種材料皆與CMOS製程相容，且 LPCVD 沉積的非晶矽和 ALD沉積的二氧化鉿皆具有良好的階梯覆蓋率。
在雙層垂直電阻式記憶體的實驗中我們可以看到元件可獨立操作，彼此在讀寫時不會互相干擾，且上下兩個電阻式記憶體之I-V特性也相近，較薄的二氧化鉿厚度有著較小的 set voltage 和較佳的耐久力；另外非晶矽薄膜垂直電阻式記憶體在連續操作後仍可維持足夠的記憶窗口，元件的記憶保持力也沒有問題，從結果可以看到較薄的非晶矽薄膜較適合拿來當作垂直電阻式記憶體的介電層。

摘要(英)

The essential structure of resistive-switching random access memory (RRAM) could be fabricated on capacitor-like metal/insulator/semiconductor (MIS) or metal/insulator/metal (MIM) stack. The simple structure is promising for development of high density nonvolatile memory (NVM). This research focused on increasing the storage density of RRAM by fabricating vertical structure which including double-layered structure to enhance the improvement of bit-per-area more efficiently.
There are two main sections in this thesis. The HfO2-based double-layered vertical RRAM (VRRAM) will be demonstrated in the first section with different dimension and thickness of HfO2 switch layer. In the second section, we demonstrated an amorphous-silicon-based VRRAM with different thickness of a-Si. HfO2 and a-Si are both compatible with CMOS fabrication process and which are also possessed of superior step coverage to fulfill the vertical structure.
Independent access between different bottom electrodes could be achieved in double-layered VRRAM which accomplished multi-bit operation. The characteristic of the two adjacent cells in the same vertical stack are identical due to excellent program/read disturbance immunity. The HfO2-based VRRAM could achieve lower set voltage (Vset) and better endurance with thinner HfO2 switch layer. The endurance and retention of amorphous-silicon-based VRRAM are both satisfactory with appropriate thickness of a-Si.

關鍵字(中)

★ 三維
★ 多位元
★ 電阻式記憶體

關鍵字(英)

論文目次

目錄
摘要 i
Abstract ii
誌謝 iv
目錄 vi
圖目錄 xi
表目錄 xvi
第一章緒論 1
1-1 前言 1
1-2 研究動機 3
第二章簡介 4
2-1 記憶體簡介 4
2-1-1 鐵電記憶體(FeRAM) 5
2-1-2 磁阻式記憶體(MRAM) 6
2-1-3 相變化記憶體(PRAM) 7
2-1-4 電阻式記憶體(RRAM) 9
2-2電阻式記憶體介紹 11
2-2-1 電阻轉換現象 11
2-2-2 電阻式記憶體量測種類 16
2-3 電阻轉換現象機制 18
2-3-1 金屬離子的電化學效應(Electrochemical metallization effect) 21
2-3-2 價電子轉換效應(Valance change effect) 24
2-3-3 熱化學效應(Thermochemical effect) 25
2-4電阻式記憶體材料 26
2-4-1 多元金屬氧化物 26
2-4-2 過渡金屬氧化物 28
2-4-3 Si 相關材料 30
2-4-4 有機材料 31
2-5 三維式快閃記憶體 34
第三章.儀器介紹與實驗流程 37
3-1機台簡介 37
3-1-1 Wet bench 37
3-1-2 自動化光阻塗佈及顯影系統(Track) 38
3-1-3 光學步進機(Canon FPA-3oooi5+ Stepper) 38
3-1-4 Lift-off 製程 39
3-1-5 TCP 9400&TCP 9600 39
3-1-6 TEL 5000 40
3-1-7 Mattson& Fusion Ozone 41
3-1-8 原子層沉積系統(ALD) 41
3-1-9 金屬快速升溫退火爐(RTA) 43
3-1-10 水平爐管 43
3-2 電性量測儀器 44
3-3 製程步驟 45
3-3-1 雙層垂直電阻式記憶體 46
3-3-2 垂直電阻式記憶體 47
第四章雙層垂直電阻式記憶體實驗結果與討論 49
4-1 以原子層沈積製作之二氧化鉿薄膜特性分析 52
4-2 微縮量測 60
4-3 DBIE 66
4-4 不同介電層厚度及不同元件面積對元件的影響 67
第五章垂直式電阻式記憶體實驗結果與討論 72
5-1 不同厚度之非晶矽薄膜特性分析 73
第六章結論與未來展望 83
6-1 結論 83
6-2 未來展望 84
參考文獻 85

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指導教授

周正堂、李耀仁
(Cheng-Tang Chou、Yao-Jen Li)

審核日期

2013-7-15

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