氮化鋁/氮化鎵/氮化鋁銦場效電晶體設計及製程

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：32

、訪客IP：3.129.211.87

姓名

葉詩恩(Shih-En Yeh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

氮化鋁/氮化鎵/氮化鋁銦場效電晶體設計及製程
(Design and Fabrication of AlN/GaN/InAlN Field Effect Transistor)

相關論文

★ 電子式基因序列偵測晶片之原型	★ 增強型與空乏型砷化鋁鎵/砷化銦鎵假晶格高電子遷移率電晶體: 元件特性、模型與電路應用
★ 使用覆晶技術之微波與毫米波積體電路	★ 注入增強型與電場終止型之絕緣閘雙極性電晶體佈局設計與分析
★ 以標準CMOS製程實現之850 nm矽光檢測器	★ 600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計
★ 具有低摻雜Ｐ型緩衝層與穿透型Ｐ＋射源結構之600V穿透式絕緣閘雙極性電晶體	★ 雙閘極金氧半場效電晶體與電路應用
★ 空乏型功率金屬氧化物半導體場效電晶體設計、模擬與特性分析	★ 高頻氮化鋁鎵/氮化鎵高速電子遷移率電晶體佈局設計及特性分析
★ 氮化鎵電晶體 SPICE 模型建立與反向導通特性分析	★ 加強型氮化鎵電晶體之閘極電流與電容研究和長時間測量分析
★ 新型加強型氮化鎵高電子遷移率電晶體之電性探討	★ 氮化鎵蕭特基二極體與高電子遷移率電晶體之設計與製作
★ 整合蕭特基p型氮化鎵閘極二極體與加強型p型氮化鎵閘極高電子遷移率電晶體之新型電晶體	★ 垂直型氧化鎵蕭特基二極體於氧化鎵基板之製作與特性分析

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文主要針對在藍寶石基板上進行氮化鋁/氮化鎵/氮化鋁銦異質結構研究，場效電晶體設計，並進行不同閘極結構製程分析。
場效電晶體設計上，使用Silvaco TCAD模擬軟體來設計新穎的氮化鋁/氮化鎵/氮化鋁銦電晶體，確認二微電子雲( 2DEG )通道的存在，與源極及汲極區低電阻的特性改善。
在氮化鋁/氮化鎵/氮化鋁銦電晶體閘極製程上，做了三種不同的製程方法，分別為蕭特基閘極電晶體、金屬氧化物半導體電晶體、閘極掘入金屬氧化物半導體電晶體，分別探討分析三種不同製程在電性上的差異。元件在閘極長度為2 m、源極至汲極距離為12 m尺寸下，蕭特基閘極電晶體的臨界電壓為-5.5 V、汲極飽和電流IDSS為125 mA/mm、導通電阻為7.2 mΩ-cm2;金屬氧化物半導體電晶體相較蕭特基閘極電晶體則需要-7 V臨界電壓將元件關閉，而汲極電流提升至150 mA/mm、導通電阻降低為5 mΩ-cm2；閘極掘入金屬氧化物-導體電晶體的臨界電壓和金屬-氧化物-半導體電晶體相較從-7 V往右移至-3 V，電流降低為100 mA/mm、導通電阻為8 mΩ-cm2。

摘要(英)

This thesis presents the study on epi-taxial layers and field-effect transistors based on AlN/GaN/InAlN grown on sapphire substrate .Transistor with different gate structures were also discussed.
Silvaco TCAD was used to design and simulate the field effect transistor for the location of 2DEG and improvement in source/drain resistance.
There were three different AlN/GaN/InAlN FET device structures in this study including Schottky gate FET, metal-oxide-semiconductor FET, and gate recess metal-oxide-semiconductor FET. The gate length of the fabricated device is 2 m and the distance between source and drain contacts is 12 m. The threshold voltage of the Schottky gate FET is -5.5 V, the on-state drain current is 125 mA/mm, and the turn on resistance is 7.2 mΩ-cm2. The threshold voltage of the metal-oxide-semiconductor FET is -7 V, the on-state drain current is 150 mA/mm, and the turn on resistance is 5 mΩ-cm2. The threshold voltage of the gate recess metal-oxidesemiconductor FET is -3 V, the on-state drain current is 100 mA/mm, the turn on resistance is 8 mΩ-cm2.

關鍵字(中)

★ 氮化鎵
★ 氮化鋁

關鍵字(英)

論文目次

目錄
摘要............ I
ABSTRACT II
致謝.............. III
目錄............. IV
圖目錄.... VI
表目錄..... IX
第一章氮化鎵材料特性和發展趨勢 1
1.1前言 1
1.2 氮化鎵材料特性與市場應用 1
1.3 增強型氮化鎵電晶體相關研究成果與研究動機 5
1.4 論文架構 9
第二章新型氮化鋁/氮化鎵/氮化鋁銦電晶體結構設計模擬與材料特性 10
2.1前言 10
2.2 氮化鋁/氮化鎵/氮化鋁銦磊晶結構設計與模擬 10
2.3 氮化鋁/氮化鎵/氮化鋁銦試片材料特性 21
試片NM130422 TLM量測結果如下: 23
2.4結論 24
第三章空乏型與增強型氮化鋁/氮化鎵/氮化鋁銦電晶體製程介紹 25
3.1 前言 25
3.2 場效電晶體光罩介紹 25
3.3氮化鋁/氮化鎵/氮化鋁銦金氧半電晶體製作流程 26
3.4閘極掘入氮化鋁/氮化鎵/氮化鋁銦金氧半電晶體製作流程 36
3.5結論 38
第四章氮化鋁/氮化鎵/氮化鋁銦電晶體元件特性分析 40
4.1 前言 40
4.2 蕭特基閘極電晶體之電流-電壓特性分析 40
4.3金屬氧化物半導體電晶體之電流-電壓特性分析 47
4.4蕭特基閘極電晶體與閘極掘入金屬氧化物半導體電晶體動態電阻分析 50
4.5閘極掘入金屬氧化物半導體電晶體之電流-電壓特性分析 54
4.6結論 58
參考文獻 60

參考文獻

參考文獻
[1] H-S. Lee, D. Piedra, M. Sun, X. Gao, S. Guo, T. Palacios, “3000-V 4.3-mΩ•cm2 InAlN/GaN MOSHEMTs,” IEEE Electron Device Lett., vol.33, no.7, pp.982-984, Jul. 2012.
[2] D. Balaz, Current Collapse and Device Degradation in AlGaN/GaN Heterostructure Field Effect Transistors, University of Glasgow, 2010.
[3] A. L. Corrion, K. Shinohara, D. Regan, I. Milosavljevic, P. Hashimoto, P. J. Willadsen, A. Schmitz, D. C. Wheeler, C. M. Butler, D. Brown, S. D. Burnham, M. Micovic, “Enhancement-Mode AlN/GaN/AlGaN DHFET With 700-mS/mm gm and 112-GHz fT,” IEEE Electron Device Lett., vol.31, no.10, pp.1116-1118, Oct. 2010.
[4] T.Oka, Nozawa, “AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications,” IEEE Electron Device Lett., vol.29, no.7, pp.668-670, Jul. 2008.
[5] C. Y. Chang, S. J. Pearton, C. F. Lo, F. Ren, I. I. Kravchenko, A. M. Dabiran, A. M. Wowchak, B. Cui, P. P. Chow, “Development of enhancement mode AlN/GaN high electron mobility transistors,” Appl. Phys. Lett., vol.94, issue.26, pp.263505-263505-3, Jun. 2009.
[6] Panasonic, Matsushita Electric (Panasonic) Develops A New Gallium Nitride (GaN) Power Transistor with Normally-off Operation, 2006.
[7] R. Chu, A. Corrion, M. Chen, R. Li, D. Wong, D. Zehnder, B. Hughes, K. Boutros, “1200-V Normally Off GaN-on-Si Field-Effect Transistors With Low Dynamic ON-Resistance,” IEEE Electron Device Lett., vol.32, no.5, pp.632-634, May. 2011.
[8] B. Lu, M. Sun, T. Palacios, “An Etch-Stop Barrier Structure for GaN High-Electron -Mobility Transistors,” IEEE Electron Device Lett., vol.34, no.3, pp.369-371, Mar. 2013.
[9] F. Medjdoub, J. Derluyn, K. Cheng, M. Leys, S. Degroote, D. Marcon, D. Visalli, M. V. Hove, M. Germain, G. Borghs, “Low On-Resistance High-Breakdown Normally Off AlN/GaN/AlGaN DHFET on Si Substrate,” IEEE Electron Device Lett., vol.31, no.2, pp.111-113, Feb. 2010.
[10] I. Hwang, J. Kim, H. S. Choi, H. Choi, J. Lee, K. Y. Kim, Jong-Bong Park, J. C. Lee, J. Ha, J. Oh, J. Shin, U-In Chung, “p-GaN Gate HEMTs With Tungsten Gate Metal for High Threshold Voltage and Low Gate Current,” IEEE Electron Device Lett., vol.34, no.2, pp.202-204, Feb. 2013.
[11] D. Morgan, M. Sultana, H. Fatima, S. Sugiyama, Q. Fareed, V. Adivarahan, M. Lachab, A. Khan, “Enhancement-Mode Insulating-Gate AlInN/AlN/GaN Heterostructure Field-Effect Transistors with Threshold Voltage in Excess of +1.5 V,”Appl. Phys. Express., vol, p.114101, 2011.
[12] I. B. Rowena, S. L. Selvaraj, T. Egawa, “Buffer Thickness Contribution to Suppress Vertical Leakage Current With High Breakdown Field (2.3 MV/cm) for GaN on Si,” IEEE Electron Device Lett., Vol. 32, no.11, pp. 1534 - 1536, Nov. 2011.
[13] R. Wang, G. Li, O. Laboutin, Y. Cao, W. Johnson, G. Snider, P. Fay , D. Jena, H. Xing, “210-GHz InAlN/GaN HEMTs With Dielectric-Free Passivation,” IEEE Electron Device Lett., Vol. 32, no.7, pp. 892 - 894, Jul. 2011.
[14] D. S. Lee, X. Gao, S. Guo, T. Palacios, “InAlN/GaN HEMTs With AlGaN Back Barriers,” IEEE Electron Device Lett., Vol. 32, no.5, pp. 617 - 619, May. 2011.
[15] D. S. Kim, K. S. Im, H. S. Kang, K. W. Kim, S. B. Bae, J. K. Mun, E. S. Nam, J. H. Lee, “Normally-Off AlGaN/GaN Metal–Oxide–Semiconductor Heterostructure Field-Effect Transistor with Recessed Gate and p-GaN Back-Barrier,” Jpn. J. Appl. Phys., Vol. 51, pp. 034101-1 - 034101-5, 2012.
[16] T.Oka, Nozawa, “AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications,” IEEE Electron Device Lett., vol.29, no.7, pp.668-670, Jul. 2008.
[17] T. Huang, X. Zhu, K. M. Wong, K.M. Lau, “Low-Leakage-Current AlN/GaN MOSHFETs Using Al2O3 for Increased 2DEG,” IEEE Electron Device Lett., vol.33, no.2, pp.212-214, Feb. 2012.
[18] T. Zimmermann, D. Deen, Y. Cao, J. Simon, P. Fay, D. Jena, H. G. Xing, “AlN/GaN Insulated-Gate With 2.3 A/mm Output Current and 480 mS/mmTransconductance,” IEEE Electron Device Lett., vol.29, no.7, p.661-664, Jul. 2008.
[19] T. Zimmermann, D. Deen, Y. Cao, D. Jena, H. G. Xing, “Formation of ohmic contacts to ultra-thin channel AlN/GaN HEMTs,” Phys. Stat. Sol.(c), vol.6, issue.6, pp. 2030 - 2032, 2008.
[20] C. Mizue, Y. Hori, M. Miczek, T. Hashizume, “Capacitance–Voltage Characteristics of Al2O3/AlGaN/GaN Structures and State Density Distribution at Al2O3 /AlGaN
Interface,” Jpn. J. Appl. Phys., vol. 50, issue.2, pp.021001-021001-7, Feb. 2011.
[21] M. A. Khan, M. S. Shur, G. Simin, “Strain-engineered novel III-N electronic devices with high quality dielectric/semiconductor interfaces,” Phys. Stat. Sol.(a), vol.200, issue.1, pp.155-160, Nov. 2003.
[22] J. Kuzmík, G. Konstantinidis, S. Harasek, S. Hascík, E. Bertagnolli, A. Georgakilas, D. Pogany, “ZrO2/(Al)GaN metal–oxide–semiconductor structures: characterization and application, ” Semicond. Sci. Technol., vol.19, pp.1364-1368, Oct. 2004.
[23] S. A. bermann, G. Pozzovivo, J. Kuzmik, G. Strasser, D. Pogany, J-F Carlin, N. Grandjean , E. Bertagnolli, “MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs,”Semicond. Sci. Technol.,vol.22, no.12, pp.1272-1275, 2007.
[24] Tuomo.suntola, “Atomic Layer Epitaxy,” Material Science Reports, vol.4, 1989.
[25] D. J. Ruzyllo, “Atomic Layer Deposition ( ALD) ,” Material Science Reports, 2006.
[26] J. Son, V. Chobpattana, Brian M, McSkimming, S.Stemmer, “Fixed charge in high-k/GaN metal-oxide-semiconductor capacitor structures,” Appl. Phys. Lett., vol. 101, issue.10, pp.102905, Sep. 2012.
[27] D. Basak, M. Verd ´ u, M. T. Montojo, M. A. S´anchez-Garcia, F J. Sanchez, E Mu ˜noz, E.Calleja, “Reactive ion etching of GaN layers using SF6,” Semicond. Sci. Technol., vol. 12, pp.1654-1657, Sep. 1997.
[28] J. Kotani, M. Tajima, S. Kasai, T. Hashizume, “Mechanism of surface conduction in the vicinity of schottky gates on AlGaN/GaN heterostructures,” Appl. Phys. Lett., vol. 91, issue.9, Aug. 2007.
[29] N. I. Kuznetsov, A. E. Nikolaev, A. S. Zubrilov, Y. V. Melnik, V. A. Dmitriev, “Insulating GaN: Zn layers grown by hydride vapor phase epitaxy on SiC substrates,” Appl. Phys. Lett., vol. 75, issue.20, pp.3138, Nov. 1999.
[30] J. B.Webb, H. Tang, S. Rolfe, J. A. Bardwell, “Semi-insulating C-doped GaN and high-mobolity AlGaN/GaN heterostructures grown by ammonia molecular beam epitaxy,” Appl. Phys. Lett., vol. 75, no.7, pp.953-955, Aug. 1999.
[31] S. Arulkumaran, T. Egawa, H. Ishikawa, T. Jimbo, “Surface passivation effects on AlGaN/GaN High-electron-mobility transistors with SiO2, Si3N4, and silicon oxynitride, ” Appl. Phys. Lett., vol. 84, no.4, pp.613-615, Jan. 2004.
[32] J. Bernat, P. Javorka, A. Fox, M. Marso, H. Luth, P. Kordos, “Effects of surface passivation on performance of AlGaN/GaN/Si HEMTs,”Solid-Statte Electron., vol. 47, issue.11, pp.2097-2103, Nov. 2003.
[33] R. A. Davies, D. J. Bazley, S. K. Jones, H. A. Lovekin, W. A. Phillips, R. H. Wallis, J. C. Birbeck, T. Martin, M. J. Uren, “The gate-length dependent performance of AlGaN/GaN HFETs with silicon nitride passivation,” Proceedings of the 8th IEEE International Symposium on High Performance EDMO, vol.76, 2000.
[34] X. Z. Dang, E. T. Yu, E. J. Piner, B. T. McDermott, “Influence of surface processing and passivation on carrier concentrations and transport properties in AlGaN/GaN hetrostructires,” J. Appl. Phys., vol. 90, issue.3, pp.1357 - 1361, Aug. 2001.
[35] D. Jin, Jesús A, d. Alamo, “Mechanisms responsible for dynamic ON-resistance in GaN high-voltage HEMTs,” Power Semiconductor Devices and ICs (ISPSD), pp.333- 336, Jun. 2012.
[36] S. Huang, Q. Jiang, S. Yang, C. Zhou, K. J. Chen, “Effective Passivation of AlGaN/GaN HEMTs by ALD-Grown AlN Thin Film,” IEEE Electron Device Lett., Vol.33, pp.516-518 , 2012.
[37] J.B.I, W.J.Schaffi I, G.H.Martin I, L.F.Eastman I, H.Amano, I.Akasakf, “Recessed Gate GaNMODFETs,”Solid-Statte Electron., Vol. 41, pp.247-250, 1997.

指導教授

辛裕明

審核日期

2013-7-31

推文