考慮佈局效應的類比設計自動化工具

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姓名

廖于晴(Yu-ching Liao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

考慮佈局效應的類比設計自動化工具
(A Layout-Aware Analog Synthesis Environment on Laker)

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摘要(中)

隨著製程的演進，電路佈局(Layout)所產生的寄生效應對於電路效能的影響也越來越顯著，然而在傳統類比電路自動化設計工具中，元件尺寸調整與電路佈局大多分成兩個獨立的流程，因為寄生效應對於電路效能的影響並未考慮進去，導致耗費了相當多的時間重複調整設計。本篇論文提出一套考量寄生效應的類比積體電路自動化設計工具，可經由操作客製化的圖形介面，設計出符合需求規格的電路設計與電路佈局。為了讓尺寸調整與電路佈局達到最佳的連結，本論文在考量寄生效應的尺寸調整流程中，使用佈局樣板預估出寄生電阻電容值，並結合電壓驅動設計方法，避免佈局後的電路效能不符合訂定之規格。整套類比自動化工具在LINUX上實現，在線性規劃(linear programming)的部分用CPLEX來找尋最佳解，而在自動產生電路佈局上則是以C/C++及Tcl/Tk 程式語言實現，自動化佈局的過程能在Laker環境下執行。從實驗數據的觀察可知，本論文所提出的工具可以在非常短的時間內設計出符合使用者所給定規格之電路與最佳的擺放佈局，並在佈局後電路效能皆有達到訂定規格的標準，且不需預留設計的邊界。

摘要(英)

In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this thesis, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. The proposed sizing algorithm has been implemented with the optimization tool CPLEX, incorporating with an automatic layout generation tool implemented with C/C++ and Tcl/Tk on Laker. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.

關鍵字(中)

★ 類比寄生效應
★ 類比自動化工具

關鍵字(英)

論文目次

摘要 i
Abstract ii
Contents iii
List of Figures v
List of Tables ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Related Works 3
1.2.1 Parasitic-Aware Performance Analysis 3
1.2.2 Analog Layout Generation Tool 5
1.3 Organization 7
Chapter 2 Background 8
2.1 Bias-driven Circuit Sizing Approach 8
2.1.1 Bias-driven performance equations 9
2.1.2 Building models and transistor sizing 11
2.1.3 Bias-driven optimization flow 15
2.2 Layout Generation with Laker 19
2.2.1 Laker and Tcl/Tk 19
2.2.2 MOS Generator 20
2.2.3 Resistor and Capacitor 21
2.2.4 Guard Ring 25
2.2.5 Layout Template 26
Chapter 3 Layout-Aware Sizing Flow 28
3.1 Parasitic in the Layout Template 29
3.2 Layout-Aware Performance Analysis 32
Chapter 4 Graphical User Interface 38
Chapter 5 Experimental Results 45
Chapter 6 Conclusion and Future Works 57
References 58

參考文獻

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指導教授

劉建男(Chien-nan Liu)

審核日期

2013-8-5

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