應用於逐漸逼近式類比數位轉換器電容陣列區塊實體佈局實現之寄生效應分析

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姓名

陳聖文(Sheng-wen Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於逐漸逼近式類比數位轉換器電容陣列區塊實體佈局實現之寄生效應分析
(Parasitic Analysis in Physical Layout Implementation for a Charge Redistribution Successive Approximation Analog-to-Digital Converter)

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摘要(中)

積體電路隨著時代的演進，在實體佈局的排列繞線上會因為金屬互連線的關係產生寄生效應。寄生效應對積體電路運作時產生的雜訊干擾、功率損耗、訊號傳遞延遲等效應，皆因製成微縮的關係，開始對電路功能的可靠度造成更顯著的影響。因此，如何在積體電路設計的過程中，考量到製成變異，並且可分析金屬互連線產生的相關寄生效應對積體電路的影響，已成為積體電路設計與量產可行性研究領域中一項具有挑戰性的重要議題。
逐漸逼進式類比數位轉換器是一種低成本、低功耗、中等速率且在工業上廣泛受歡迎。本論文針對電荷重分佈逐漸逼進式類比數位轉換器的電容陣列區塊繞線後的寄生效應進行分析，提出電容陣列區塊的寄生模型。而此等效的寄生模型則是由完整連接的耦合電容推導而來。根據逐漸逼近式類比數位轉換器的三種操作模式，採樣、保持、比較來做分析，推斷出只有並聯在單位電容的平行寄生電容和上極板對基底的寄生電容，來對這些電容比例做一個評估。因此，積分非線性誤差INL的最差情況會因為寄生效應的關係發生在輸出樣本全為一的時候。

摘要(英)

For the advancement of integrated circuit technology, the parasitic effects of interconnects need to be considered on the physical layout of routing and placement. From the physical scaling, the parasitic effects like noise interference, power consumption and signal propagation delay have begun to have the significant impact on the reliability and function of analog integrated circuit. Therefore, how to take the parasitic effects of interconnects into the design flow of analog integrated circuit has become a challenging study issue.
SAR ADC is a low cost, low power, medium speed ADC which is very popular in industry. In this thesis, the research aims to analyze the parasitic effects in the capacitor array block and results in an equivalent parasitic model for a charge-redistribution SAR ADC. The equivalent parasitic model is derived starting from the fully connected coupling capacitances. According to the operations in three modes, sampling, hold and comparing, it is deduced that only the parasitic capacitance of totally connected top-plate to substrate and the parallel parasitic capacitances of each MiM capacitor are remained for the evaluation of capacitance ratios. Consequently, the worst case of integral nonlinearity INL due to the parasitics is concluded and occurs in the pattern of all ones.

關鍵字(中)

★ 寄生效應
★ 電容陣列
★ 逐漸逼進式類比數位轉換器

關鍵字(英)

★ SAR ADC
★ Parasitic
★ Physical Layout

論文目次

中文摘要 i
Abstrast ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
Chapter 1. 緒論 1
1.1動機與背景 1
1.2論文組織 3
Chapter 2. SAR ADC的基本概念 4
2.1類比數位轉換器基本原理 4
2.2 SAR ADC的架構與運算 6
2.3類比數位轉換器的特性參數 11
Chapter 3. 電容陣列的擺放與繞線 16
3.1 電容佈局設計的概念 17
3.1.1電容之簡介 17
3.1.2電容不匹配的原因 20
3.1.3電容匹配的規則 21
3.2共質心(Common-Centroid) 24
3.3電容陣列的繞線 27
3.3.1積體電路繞線考量與設計規範(Design rule) 27
3.3.2地鐵式繞線法(Subway Routing) 30
Chapter 4. 寄生電容模型與實驗分析 34
4.1寄生電容參數總類 34
4.1.1本質對地寄生電容分析 36
4.1.2導線間寄生電容分析 37
4.1.3繞線的寄生電容分析 38
4.2 SAR ADC寄生電容模組建立與效應分析 41
4.3寄生電容值的評估與計算 49
4.4 SAR ADC Worst case分析 54
4.5 SAR ADC 行為模擬與實驗結果 58
Chapter 5. 結論 63
參考文獻 64

參考文獻

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指導教授

陳竹一(Jwu-e Chen)

審核日期

2013-11-28

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