博碩士論文 100521031 完整後設資料紀錄

DC 欄位	值	語言
DC.contributor	電機工程學系	zh_TW
DC.creator	江哲君	zh_TW
DC.creator	Che-Chun Chiang	en_US
dc.date.accessioned	2013-11-28T07:39:07Z
dc.date.available	2013-11-28T07:39:07Z
dc.date.issued	2013
dc.identifier.uri	http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=100521031
dc.contributor.department	電機工程學系	zh_TW
DC.description	國立中央大學	zh_TW
DC.description	National Central University	en_US
dc.description.abstract	對於在類比積體電路電容器的實現，它是連接對應於總量的單元電容器。互連的寄生電容大大地影響了電容比率並且導致性能的退化。因此，寄生電容需要考慮和良好的控制。在這篇論文中，Subway繞線，其擺置互連在MIM電容下，加入了我們的電容陣列塊創（CABC）。它具有多種強大的功能，包括績效補償和降低錯配和更低的面積，進步良率高。 兩個電路的例子，8-位元SAR ADC和弗萊舍 - 湖人開關電容濾波器，用於演示的性能Subway繞線器。結果表明，在這兩個電路中，電容率是良好匹配，並比以前更好的性能。	zh_TW
dc.description.abstract	For the implementation of capacitors in the analog integrated circuits, it is to connect the unit capacitors corresponding to the total amount. The parasitic capacitance of interconnects greatly affects the Capacitance Ratio and induces the performance degradation. Hence, parasitic capacitances need to be considered and well controlled. In this thesis, a subway routing style, which places the interconnects under the MiM capacitors, is proposed for our capacitor array block creators (CABC). It exhibits several powerful features including performance compensation and mismatch reduction and with less area, in turns, high yield. Two circuit examples, 8-bit SAR ADC and Fleischer-Laker switched-capacitor filter, are used to demonstrate the performance of subway router. It is shown that, in both circuits, capacitance ratios are good matched and better performance than the previous.	en_US
DC.subject	電容陣列	zh_TW
DC.subject	類比繞線	zh_TW
DC.subject	Capacitor Array	en_US
DC.subject	Analog Router	en_US
DC.title	應用於電容陣列區塊之良率導向地鐵式繞線法	zh_TW
dc.language.iso	zh-TW	zh-TW
DC.title	Subway-CABC: A Yield-aware Subway Router for Capacitor Array Block Creation	en_US
DC.type	博碩士論文	zh_TW
DC.type	thesis	en_US
DC.publisher	National Central University	en_US