| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 邱怡菁 | zh_TW |
| DC.creator | Yi-ching Chiu | en_US |
| dc.date.accessioned | 2013-8-12T07:39:07Z | |
| dc.date.available | 2013-8-12T07:39:07Z | |
| dc.date.issued | 2013 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=100521096 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文題目為應用於K/V頻段之低功耗CMOS低雜訊放大器之研究。主要在探討低雜訊放大器的低功耗設計方式，提出了四個實現低功耗特性的不同電路。
本論文採用tsmcTM CMOS 0.18 µm 1P6M製程，設計兩個電路：第一個電路為應用於K頻段之低功耗低雜訊放大器。本電路的重點在於如何降低功耗。設計方式為使用基體順向偏壓與電流再利用技術來降低功率消耗，同時使用源極退化增加電路整體線性度。電路量測結果在27 GHz時有最大增益值為5.0 dB，輸入與輸出反射損耗分別為14.9 dB與12.2 dB，雜訊指數為7.3 dB，輸入增益1 dB壓縮點與輸入三階交互調變交叉點為-15 dBm與-3 dBm，功率消耗為9.5 mW，晶片面積為0.64 mm2。第二個電路為一個使用變壓器回授之低功耗低雜訊放大器。本電路的重點在於如何在應用範圍(18~26 GHz)內有效提升增益與降低功耗。設計方式為使用變壓器回授降低功率消耗，並提升電路整體線性度。電路量測結果在23.1 GHz時有最大增益值為8.4 dB，輸入與輸出反射損耗分別為36.2 dB與37.1 dB，雜訊指數為5.4 dB，輸入增益1 dB壓縮點與輸入三階交互調變交叉點為-11 dBm與-3 dBm，功率消耗為4.7 mW，晶片面積為0.436 mm2。
採用tsmcTM CMOS 90 nm 1P9M製程，設計兩個電路：第一個電路為應用於V頻段之低功耗達靈頓低雜訊放大器。本電路的重點在於如何在應用範圍(57~64 GHz)內有效提升增益與降低功耗。設計方式為使用達靈頓對電晶體架構。電路量測結果在55.5 GHz時有最大增益值為3.8 dB，輸入與輸出反射損耗分別為3.1 dB與11.7 dB，雜訊指數為10.3 dB，輸入增益1 dB壓縮點與輸入三階交互調變交叉點為-10 dBm與-1 dBm，功率消耗為12.9 mW，晶片面積為0.531 mm2。第二個電路為應用於V頻段之低功耗低雜訊放大器。本電路的重點在於如何在應用範圍(57~64 GHz)內有效提升增益與降低功耗。設計方式為使用共閘極電晶體架構與電流再利用技術來降低功率消耗。電路量測結果在56.6 GHz時有最大增益值為7.6 dB，輸入與輸出反射損耗分別為27.4 dB與22.7 dB，雜訊指數為9.0 dB，輸入增益1 dB壓縮點與輸入三階交互調變交叉點為-14 dBm與-4 dBm，功率消耗為12.1 mW，晶片面積為0.501 mm2。 | zh_TW |
| dc.description.abstract | The title of this thesis is ＂Study of Low-Power CMOS Low-Noise Amplifier for K and V-Band Applications.＂ The thesis focuses on the design of low-noise amplifier used in low-power consumption, which include the four different circuits.
The circuits are implemented with tsmcTM CMOS 0.18-μm 1P6M process. The first circuit is a low-power low-noise amplifier for K-band Applications. The emphasis of this circuit is how to reduce the power consumption. The design approach to reduce the power consumption is forward body bias and current-reused technologies, while increasing the overall linearity using source degeneration. The measured results of the designed circuits are illustrated as followings. The LNA achieved a measured maximum gain of 5.0 dB at 27 GHz; the input and output return loss is 14.9 dB and 12.2 dB, respectively. The measured minimum noise figure is 7.3 dB. The input 1-dB gain compression point is -15 dBm and third-order intermodulation terms is -3 dBm. The total power consumption is 9.5 mW. The chip area is 0.64 mm2.
The second circuit is a low-power transformer-feedback low-noise amplifier. For 18~26 GHz application, the emphasis of this circuit is how to improve gain and reduce power consumption. The design is approach for the use of the transformer-feedback to reduce power consumption and improve the linearity. The measured results of the designed circuits are illustrated as followings. The LNA achieved a measured maximum gain of 8.4 dB at 23.1 GHz. The input and output return losses are 36.2 dB and 37.1 dB, respectively. The measured minimum noise figure is 5.4 dB. The input 1-dB gain compression point is -11 dBm and third-order intermodulation terms is -3 dBm. The power consumption is 4.7 mW. The chip area is 0.436 mm2.
Two other circuits are implemented in tsmcTM CMOS 90-nm 1P9M process. The first one is aA low-power Darlington LNA for V-band applications. For 57~64 GHz application, the emphasis of the circuit is how to improve gain and reduce power consumption. The design approach is the use of Darlington pair transistor topology. Circuit measurement results at 55.5 GHz achieved a measured maximum gain of 3.8 dB. The input and output return losses are 3.1 dB and 11.7 dB. The measured minimum noise figure is 10.3 dB. The input 1-dB gain compression point is -10 dBm and third-order intermodulation terms is -1 dBm. The power consumption is totally 12.9 mW. The chip area is 0.531 mm2.
The second circuit is a low-power LNA for V-band Applications. For 57~64 GHz application, the emphasis of this circuit is how to improve gain and reduce power consumption. The design approach uses the common gate transistor structure and current-reused technologies to reduce power consumption. Circuit measurement results at 56.6 GHz achieved a measured maximum gain of 7.6 dB. The input and output return losses are 27.4 dB and 22.7 dB. The measured minimum noise figure is 9.0 dB. The input 1-dB gain compression point is -14 dBm and third-order intermodulation terms is -4 dBm. The power consumption is totally 12.1 mW. The chip area is 0.501 mm2. | en_US |
| DC.subject | 低雜訊放大器 | zh_TW |
| DC.subject | 低功耗 | zh_TW |
| DC.subject | K頻段 | zh_TW |
| DC.subject | V頻段 | zh_TW |
| DC.subject | Low-noise amplifier | en_US |
| DC.subject | Low-power | en_US |
| DC.subject | K-Band | en_US |
| DC.subject | V-Band | en_US |
| DC.title | 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Study of Low-Power CMOS Low-Noise Amplifier for K and V-Band Applications | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |