博碩士論文 100581009 完整後設資料紀錄

DC 欄位 語言
DC.contributor電機工程學系zh_TW
DC.creator王慶奇zh_TW
DC.creatorChing-Chi Wangen_US
dc.date.accessioned2017-7-27T07:39:07Z
dc.date.available2017-7-27T07:39:07Z
dc.date.issued2017
dc.identifier.urihttp://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=100581009
dc.contributor.department電機工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract本論文主題在於製備與探討矽鍺奈米結構(如量子點和奈米線)及其相關熱電元件。 矽鍺半導體材料應用於熱電應用之最大的優勢是與目前積體電路製程技術的高度相容性。本論文利用選擇性氧化矽鍺位於含矽材料之上的技術來製備可定位、定量以及可調變尺寸的三維鍺量子點陣列,並探討其光學與熱電特性。在高溫氧化矽鍺形成鍺量子點過程中,實驗觀察到在過長的氧化時間下,鍺量子點在穿越過氮化矽層,進入矽基板時會發生類似爆炸的行為,整顆量子點分散成了雲霧般的鍺團。我們提出了模型來解釋,當鍺量子點在氧化期間進入含矽層時,含矽層所釋出的矽原子流量的多寡對於掌控鍺量子點的幾何型態有重要的影響。此發現輔助了我們對鍺量子點定位和定量掌控性的認識。在光學特性部分,我們由光激發螢光譜分析觀察到鍺量子點擁有準能隙特性,且光譜上的波峰能量隨鍺量子點尺寸縮小而有藍移的現象,此歸因於量子侷限效應。熱傳導係數量測實驗發現藉由量子侷限效應,對於鍺量子點崁入二氧化矽之薄膜而言,由於奈米結構的表面聲子散射以及矽鍺本身的合金散射有效地拖曳了聲子的傳輸,使熱傳導係數大幅下降,而且此熱傳導降低的現象與鍺量子點的尺寸與反比關係。 我們亦研究開發矽鍺奈米柱狀結構,並特討其熱電性質。實驗觀察到鍺莫耳比12-36%的矽鍺奈米柱的的熱傳導係數約在0.8-2 W/m•K,且隨著鍺濃度的提升而有下降的趨勢。在電傳導係數方面,不論是N-type和P-type矽鍺奈米柱皆隨著鍺濃度的增加而上升,此歸因於等效質量的降低因而增強載子遷移率。由此可見,矽奈米柱加入鍺確實可以分別調整聲子與載子的傳輸表現。 在矽鍺奈米柱致冷元件中,我們使用矽鍺化鎳奈米線做為矽鍺奈米柱的底部電連結。由於熱電致冷元件在運作時,常需注入高電流或高偏壓,因此我們需詳加了解矽鍺化鎳奈米矽線的電連結在高電流或是高電壓的操作條件下的熱穩定性。為了瞭解矽鍺化鎳奈米線的電氣特性,首要之務是其晶相的控制。因此,我們先對不同幾何大小矽奈米線的鎳化反應進行探討。實驗發現矽化鎳奈米線的晶體相位、幾何體積膨脹以及電阻率與矽奈米線的幾何尺寸有著緊密的關係。在鎳化反應溫度為500oC的條件下,矽奈米線寬度範圍為250-450 nm之間,其矽化鎳相位為NiSi,所對應的電阻值約為12.5 -cm;但是當矽奈米線寬度範圍微縮至40-100 nm時,其矽化鎳相位則轉換為Ni2Si,電阻值上升至30 -cm。矽化鎳如此的相位產生有別於塊材矽薄膜層反應受反應溫度控制而統一形成NiSi。我們提出一新穎的塑性形變機制來解釋之。 利用電子束微影技術與電漿蝕刻實作出矽鍺奈米柱陣列(柱子寬度約250 nm/高度約1000 nm)。藉由調變不同的柱子陣列面積(17×12 μm^2、37×32 μm^2與56×52 μm^2)以及矽鍺柱子之鍺濃度(0%與24%),我們系統性的探討柱子陣列面積和鍺濃度對熱電致冷元件的致冷能力的影響。以柱子陣列尺寸面積37×32 μm2以及鍺濃度為24%矽鍺奈米柱致冷元件為例,在環境溫度為90oC的條件下,其致冷溫度可達到15oC,而致冷效率為1.36 oC/μA。zh_TW
dc.description.abstract This thesis concerns the fabrication and characterization of SiGe nanostructures (such as quantum dots (QDs) and nanowires (NWs)) as well as related thermoelectric devices. For thermoelectric application, the major advantage of SiGe-based material is the compatibility to prevailing complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) technology. We propose thermally oxidizing SiGe on Si-containing layer, for generating precise numbering, placing and size-tunable Ge QD array, and study their optical and thermoelectric properties in this thesis. Interestingly, unique ‘explosive’ behavior of Ge QDs through Si3N4 layers into the underlying Si substrate is observed during high-temperature oxidation for a long time; the QDs regress almost to their origins as individual Ge nuclei are formed during the oxidation of the original nanopatterned SiGe structures that were used for their generation. A kinetic model is proposed to explain the anomalous migration behavior and morphological changes of the Ge QDs, based on the Si flux that is generated during the oxidation of Si-containing layers. This finding enhances control over the location and quantity of Ge QDs. Moreover, we observed the transition energy of Ge QD appears to have a systematic blue-shift with a decrease in Ge QD size, indicating the transition of Ge from indirect to direct band-gap materials, thanks to quantum confinement effects. The temperature-dependent thermal conductivity of the Ge QD array is systematically investigated. The experimental results appear to reveal an inverse dependence of the thermal conductivity of Ge QDs on dot size in a SiO2 system. Clearly, surface/boundary scattering of nanostructures and alloy scattering cause phonon drag and considerably reduce thermal conductivity, owing to quantum confinement. The thermoelectric properties of Si1-xGex nanopillars were systematically investigated. The thermal conductivities of Si1-xGex nanopillars with Ge mole fractions of 0.12-0.36 are between 0.8 and 2 W/m•K, and depend inversely on Ge content. An increase in the Ge content significantly increases the electrical conductivity of both N- and P-type Si1-xGex NWs, because of a reduction in the effective mass and, therefore, an increase in carrier mobility. The inclusion of Ge into the nanopillar structures can support the decoupling of the resistances to phonon and charge transport. NiSi1-xGex nanocontacts are used to connect pairs of N- and P-type pillars at the bottom of each in the Si1-xGex microcooler. Therefore, obtaining a detailed understanding of the thermal stability, electrical property and phase formation of NiSi1-xGex NWs is important due to the injected high current and voltage in Si1-xGex microcoolers. The experimental finding suggests the geometry of Si NWs is key factor to affect the phase, volumetric expansion and electrical resistivity of the NixSiy NWs. The phase transition from NiSi with large NWs (WSi NW = 250-450 nm) to Ni2Si with small NWs (WSi NW = 40-100 nm) is closely correlated associated with the observed variation in electrical resistivity with NW width after silicidation at 500oC, and the resistivities of the various NixSiy phases are NiSi - 12.5 -cm and Ni2Si - 30 -cm. Interestingly, an Ni-rich phase of the NixSiy NWs is formed, in sharp contrast to the formation of nickel monosilicide for the NiSi film. A new, plastic deformation mechanism is proposed to explain it. Electron-beam lithography and plasma etching were used to generate SiGe nanopillars with a diameter of 250 nm and a height of 1000 nm. Then, the Si1-xGex (x = 0 and 0.24) P/N-pair nanopillar arrays with sizes of 17×12 μm^2, 37×32 μm^2, and 56×52 μm^2 for use in thermoelectric microcoolers is developed. The effects of Ge content and the size of the array of SiGe nanopillars on cooling capability are systematically studied. An array of Si0.76Ge0.24 nanopillars with an area of 37×32 µm^2 exhibits a cooling efficiency as high as 1.36oC/μA at 90oC, such that cooling by more than 15oC is achieved at 90oC.en_US
DC.subject量子點zh_TW
DC.subject奈米線zh_TW
DC.subject矽鎳化物zh_TW
DC.subject熱電效應zh_TW
DC.subject微致冷器zh_TW
DC.subject矽鍺合金zh_TW
DC.subjectquantum doten_US
DC.subjectnanowireen_US
DC.subjectNiSien_US
DC.subjectthermoelectricen_US
DC.subjectmicrocooleren_US
DC.subjectSiGeen_US
DC.title應用於熱電元件之矽鍺奈米結構開發研究zh_TW
dc.language.isozh-TWzh-TW
DC.titleSiGe Nanostructures for Thermoelectric Microcooler Applicationsen_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

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