| DC 欄位 |
值 |
語言 |
| DC.contributor | 光機電工程研究所 | zh_TW |
| DC.creator | 黃永昇 | zh_TW |
| DC.creator | Yong-Sheng Huang | en_US |
| dc.date.accessioned | 2014-8-20T07:39:07Z | |
| dc.date.available | 2014-8-20T07:39:07Z | |
| dc.date.issued | 2014 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=101327006 | |
| dc.contributor.department | 光機電工程研究所 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 多重連續訊號的擷取與重建在許多系統中會使用上，例如：多點光學干涉訊號、生醫訊號、位移量測等都會用上。本實驗所使用的多重同步輸入訊號為光學干涉儀，在控制器端各通道的資料擷取必須達到同步，才可以使因訊號處理所造成的時間延遲誤差所造成的相對相位誤差減少，進而掌握位移的量測誤差。本控制器的核心使用ARM以及FPGA兩種韌體、硬體設計控制器，並對雙方的優缺點及誤差值做比較，達到同步訊號擷取的效果。
因系統對同步及量測精準度的要求，因此考慮時間延遲及量測誤差，以達到最佳之控制器設計，本研究採用EDA工具合成電路，並採用可成式燒錄之FPGA及ARM兩種硬體架構的控制器，以實驗對比兩者的同步效能，而能選用較優者。在運用FPGA硬體之電路設計採用GRAFCET架構，是由具備平行運算架構的處理器及硬體電路合成。而運用一般控制器如ARM的架構則具有程序性，同步處理可能會因為運算核心被佔用而產生延遲，擬以同步觸發控制同步輸入訊號之量測，提高精度。 實驗驗證的結果證實以FPGA建構的系統，不會有受限於系統時脈的同步誤差，只有電路訊號傳遞延遲的誤差，實測值約為11.1ns。而運用ARM內建的ADC所建構的系統，當採樣頻率在400kHz以上，會有至少一個採樣週期的通道間同步誤差。 | zh_TW |
| dc.description.abstract | The data sampling and signal capture of multiple signals for the reconstruction of original continuous functions is an important function in many instrumentation systems, for example: multi-point sensing for optical interferometry, biomedical monitoring system, and in the measurement of displacements. A multi-channel signal capturing system is developed for optical interferometry for the measurement of displacement and motion. For such a system, it is important that the signals are captured synchronously with a minimum time delay from channel to channel so as to minimize relative phase shift between channels, and, thus, the errors resultant in the displacement measurement, due to signal processing. In order to compare the achievable synchronization by different hardware architectures, a controller built with an ARM core and the other with a FPGA were developed. The FPGA is programmed by GRAFCET with parallelism, while a microcontroller like ARM executes instructions sequentially. Hence, the existence of processing delay between channels competing for processing resource is likely.
Actual tests on the FPGA implementation show that there is no channel synchronization time difference due to system clock. There is only deviations about 11.5ns due to propagation delay in the electric circuits. While there is at least one sampling time step difference between channels in the ARM implementation when the sampling rate is above 400kHz. | en_US |
| DC.subject | 可現場程式邏輯閘陣列 | zh_TW |
| DC.subject | 進階精簡化指令集 | zh_TW |
| DC.subject | 同步訊號量測 | zh_TW |
| DC.subject | FPGA | en_US |
| DC.subject | ARM | en_US |
| DC.subject | Multiple capture of continuous signals | en_US |
| DC.title | 多重訊號同步擷取裝置整合研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |