| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 楊國慶 | zh_TW |
| DC.creator | Kuo-ching Yang | en_US |
| dc.date.accessioned | 2015-1-21T07:39:07Z | |
| dc.date.available | 2015-1-21T07:39:07Z | |
| dc.date.issued | 2015 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=101521020 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文利用選擇性氧化複晶矽鍺柱/氮化矽/矽基材的結構來形成一體成型鍺奈米球/二氧化矽/矽鍺合金之金氧半異質結構。在透過元件結構的實驗設計，包含利用提升鍺奈米球的直徑大小來增加鍺奈米球的電容，以及將非鍺奈米球區域製作區域性的溝渠隔離區來降低寄生效應。成功地將鍺奈米球所貢獻的電容與周圍寄生電容的比例提升至約1比1左右，以利於提升鍺奈米球區域之介面缺陷密度萃取的準確性以評估探討介面特性。此外，本文同時製作“鋁/二氧化矽/鍺奈米球”以及“鍺化鎳/二氧化矽/矽鍺合金”之兩種金氧半電容結構，分別探討“二氧化矽/鍺奈米球”以及“二氧化矽/矽鍺合金”之間的介面品質。
透過變溫高低頻之電容-電壓量測分析，所萃取出二氧化矽/鍺奈米球之間的介面缺陷密度約3-4×1011 cm-2eV-1，二氧化矽/矽鍺合金之間的介面缺陷密度約3.5-5.5×1011 cm-2eV-1。兩者皆證明鍺/二氧化矽/矽鍺合金的介面之異質結構具有元件等級的介面品質。此外，本文透過調變鍺奈米球的大小與鑽入矽基板的深度來得以有效地控制矽鍺殼的長度與厚度，再搭配鍺奈米球介面的應力工程，有利於日後鍺通道金氧半電晶體的製作。
| zh_TW |
| dc.description.abstract | In this thesis, we demonstrated a unique approach to generate a self-organized Ge-nanoball/SiO2/SiGe heterostructure on the Si substrate through the selective oxidation of poly-Si0.83Ge0.17 nano-pillar over buffer layers of Si3N4 that were deposited over the Si substrates. In order to investigate the interface properties of this designer heterostructure, experimental designs of device structures, including increasing the diameter of Ge-nanoball to enhance the capacitance of Ge and making trench isolation to reduce the parasitic effect are employed. We are able to further increase the ratio of the capacitance contributed by Ge-nanoball to that by the surrounding parasitic capacitance to about 1：1, leading to more accurate extraction of interface trap density within Ge-nanoball region. Accordingly, we fabricate Al/SiO2/Ge-nanoball and NiGe/SiO2/SiGe metal oxide semiconductor capacitors to explore the interface quality properties between SiO2 and Ge-nanoball as well as between SiO2 and SiGe shell, respectively.
The extracted interface trap density (Dit) from temperature-dependent high- and low-frequency capacitance-voltage (C-V) characteristics was about 3-4×1011 cm-2eV-1 between SiO2 and Ge-nanoball, and about 3.5-5.5×1011 cm-2eV-1 between SiO2 and SiGe. These results indicate superior interfacial properties in the studied Ge-nanoball/SiO2/SiGe on Si heterostructure, which is a promising candidate for high-performance Ge MOSFETs.
| en_US |
| DC.subject | 鍺金氧半電容 | zh_TW |
| DC.subject | 鍺奈米球 | zh_TW |
| DC.subject | 介面工程 | zh_TW |
| DC.subject | 介面缺陷密度 | zh_TW |
| DC.subject | Ge MOS Capacitor | en_US |
| DC.subject | Ge-nanoball | en_US |
| DC.subject | interface engineering | en_US |
| DC.subject | interface trap density | en_US |
| DC.title | 自組式鍺奈米球/二氧化矽/矽鍺合金閘堆疊異質結構之介面工程最佳化探討 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Optimization on self-organized Ge-nanoball/SiO2/SiGe gate-stacking heterostructure with interface engineering | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |