| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃書彥 | zh_TW |
| DC.creator | Shu-Yan Huang | en_US |
| dc.date.accessioned | 2015-6-26T07:39:07Z | |
| dc.date.available | 2015-6-26T07:39:07Z | |
| dc.date.issued | 2015 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=101521041 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文主要著重應用於微波及毫米波的次諧波注入壓控振盪器及其運用在鎖頻迴路與應用於類比數位轉換器前端的高速追蹤與保持放大器。第二章及第三章分別闡述了次諧波注入鎖定鎖頻迴路的分析、模擬及量測結果，第四章為CMOS寬頻追蹤與保持放大器的設計與分析。
第二章介紹次諧波注入鎖定鎖頻迴路的理論模型架構，並且提出各個方塊元件的理論模型轉移函數，根據推導出來的模型架構去設計整個次諧波注入鎖定鎖頻迴路，並且用理論計算值的結果去驗證整個系統的穩定性。在製程、電壓及溫度變異下，這次所提出的次諧波注入鎖定鎖頻迴路具有高穩定性，所設計次諧波注入鎖定鎖頻迴路使用的製程是台積電提供的90 nm通用互補式金氧半場效電晶體製程。量測結果完整呈現次諧波注入鎖定振盪器、次諧波注入鎖定鎖頻迴路以及鎖相迴路。在頻率為10.4 GHz時，鎖頻迴路具有-130.38 dBc/Hz的相位雜訊，而最低的抖動量為30.3 fs，此時頻率為10.3 GHz，而電路的直流功率消耗為26 mW。
第四章為追蹤與保持放大器的設計及分析，在輸入級緩衝器方面，運用了分佈式放大器的結構來使整個追蹤與保持放大器的頻寬提升，而追蹤與保持開關的部分採用了一個額外的P型MOS來解決電荷注入效應對無失真動態範圍的影響，而輸出緩衝級採用了疊接放大器的架構，用來提升追蹤與保持放大器整體的線性度。本次設計的追蹤與保持放大器所使用的製程是台積電提供的90 nm低功耗互補式金氧半場效電晶體製程。量測的結果具有0~17 GHz的3 dB增益頻寬，而無失真動態範圍在12 GS/s以及6 GS/s分別為-42.1 dB及 -41.9 dB，直流功率消耗為216 mW。
| zh_TW |
| dc.description.abstract | This thesis focuses on the sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) for microwave and millimeter-wave applications and the high speed track-and-hold amplifier (THA) for front-end of analog-to-digital converter (ADC). The analysis, simulation and measurement of the SILVCO with FLL are presented in Chapter 2 and 3, respectively. The design and analysis of a broadband CMOS THA are proposed in Chapter 4.
The theoretical model of SILVCO with FLL are proposed in Chapter 2. The transfer functions of the other blocks in SILVCO with FLL are presented. The SILVCO with FLL is designed using the proposed model, and the calculated results are presented to verify the loop stability. The proposed SILVCO with FLL demonstrates good robustness versus process, voltage, and temperature variations. The proposed SILVCO with FLL is fabricated using TSMC 90 nm CMOS general purpose (GP) process. The measurements of the SILVCO with FLL and phase-locked loop (PLL) are completely presented. As the output frequency is 10.4 GHz, the proposed SILVCO with FLL features a phase noise of -130.38 dBc/Hz and the minimum jitter features 30.25 fs when output frequency is 10.3 GHz. The dc power consumption of the proposed SILVCO with FLL is 26 mW.
The design and analysis of the proposed THA are presented in Chapter 4. The distributed amplifier (DA) is adopted to enhance the bandwidth of the proposed THA. The dummy switch topology is also adopted in the track-and-hold stage to avoid the charge injection. The cascode amplifier is used to enhance the linearity of the proposed THA. The proposed THA is fabricated using TSMC 90 nm CMOS low power (LP) CMOS process. The proposed THA features a 3-dB bandwidth from 0 to 17 GHz. The measured spurious-free dynamic ranges (SFDR) of the proposed THA are -42.1 dB and -41.9 when the sampling rates are 12 GS/s and 6 GS/s, respectively. The dc power consumption of the proposed THA is 216 mW.
| en_US |
| DC.subject | 鎖頻迴路 | zh_TW |
| DC.subject | 追蹤與保持放大器 | zh_TW |
| DC.subject | 微波及毫米波 | zh_TW |
| DC.title | 鎖頻迴路及追蹤與保持放大器之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of Frequency-Locked Loop and Track-and-Hold Amplifier | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |