| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳宇軒 | zh_TW |
| DC.creator | Yu-hsuan Chen | en_US |
| dc.date.accessioned | 2015-8-27T07:39:07Z | |
| dc.date.available | 2015-8-27T07:39:07Z | |
| dc.date.issued | 2015 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=101521084 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 現今單晶片系統(SOC)通常擁有許多記憶體，而這些記憶體的可靠度及良率對單晶片系統的可靠度及良率有相當大的影響，因此有效提升單晶片系統內記憶體的可靠度及良率非常的重要。錯誤更正碼(ECC)是一個廣泛用來提升記憶體可靠度的技術，然而，錯誤更正碼容易發生錯誤累積效應導致記憶體無法修復，週期透明測試則可解決這個問題。在記憶體良率提升方面，內建自我修復電路(BISR)是廣泛被使用的方法。
在本論文中，我們提出了一個在隨機存取記憶體中，運用BCH碼來檢測資料完整性的內建自我透明測試電路(BIST)。此電路可識別記憶體內多重錯誤的位置。與過去所提過的方法比較，此電路可運用較小面積的校驗碼來提供較高的可靠度。模擬結果顯示此電路應用在64Kb靜態隨機存取記憶體與使用TSMC 90-nm製程時的邏輯閘數為45.3K。此外，我們同時提出一個應用於NAND快閃記憶體的內建自我修復電路。此電路包含一個內建自我修復電路及一個BCH修復電路，此內建自我修復電路分析錯誤的資訊並將錯誤的資訊儲存到所提出的備用陣列，在NAND快閃記憶體的一般操作時，BCH修復電路根據儲存在備用陣列裡錯誤資訊區塊與校驗碼區塊裡的錯誤資訊與校驗碼來修復錯誤。模擬結果顯示此電路應用在128MB NAND快閃記憶體與使用TSMC 0.13-μm製程時的邏輯閘數為12.31K。
| zh_TW |
| dc.description.abstract | Modern system-on-chip (SOC) designs usually have many memories. The reliability and yield of
SOCs thus is dominated by that of memories. Effective reliability and yield enhancement techniques
for memories in SOCs are very important. Error correction code (ECC) is one widely
used reliability-enhancement technique for memories. However, ECC technique is prone to faultaccumulation
effect. Periodic transparent test can be used to cope with the issue. On the other
hand, built-in self-repair (BISR) technique is one popular method used to enhance the yield of
embedded memories.
In the first part of this thesis, we propose a transparent built-in self-test (BIST) scheme for
random access memories using BCH code for data integrity checking. The proposed transparent
BIST scheme can identify the fault locations of multiple faults within a targeted memory block.
In comparison with existing works, the proposed transparent BIST scheme can provide higher
reliability with smaller area cost of check bits. Simulation result shows that the gate count of
transparent BIST for a 64Kb SRAM using TSMC 90-nm CMOS standard cell library is 45.3K. In
the second part of this thesis, we propose a BISR technique for embedded flash memories. The
BISR technique includes a BISR circuit and a BCH correction circuit. The BISR circuit analyzes
the fault locations and stores it in the spare array. The spare array with faulty information block
and check bits block is used to repair the faults in the normal NAND flash operations by the BCH
correction circuit. Simulation result shows that the gate count of BISR for a 128MB NAND flash
using TSMC 0.13-μm CMOS standard cell library is 12.31K. | en_US |
| DC.subject | 半導體記憶體 | zh_TW |
| DC.subject | BCH碼 | zh_TW |
| DC.subject | 可靠度 | zh_TW |
| DC.subject | 良率 | zh_TW |
| DC.subject | Semiconductor Memories | en_US |
| DC.subject | BCH Code | en_US |
| DC.subject | Reliability | en_US |
| DC.subject | Yield | en_US |
| DC.title | 應用於半導體記憶體之基於BCH碼可靠度與良率增強技術 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Reliability and Yield Enhancement Techniques for Semiconductor Memories Using BCH Code | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |