| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 何建宏 | zh_TW |
| DC.creator | Chien-hung Ho | en_US |
| dc.date.accessioned | 2014-8-27T07:39:07Z | |
| dc.date.available | 2014-8-27T07:39:07Z | |
| dc.date.issued | 2014 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=101521102 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 現今的製程已經達到奈米層級，在元件(device)上因製造(manufacture)時所產生的變異(variation)隨處可見，而這些變異大致上可區分為全域變異(global variation)及區域變異(local variation)兩種，當製程變異造成電路效能變化過大時，可能會造成電路設計失效，而導致晶片製造良率(yield)下降，因此，在晶片正式下線前需要對這些變異進行分析，以保證晶片出貨的品質。
在全域變異的考量上，結合製程(process)、電源(voltage)、溫度(temperature)之極端情況的角落分析(Corner Analysis)是廣泛被運用的，但在現今的製程中，完整的角落分析需要經過數百或數千個角落的模擬，太過耗時而變得不實用。而在區域變異方面，由於其變因相當的多，常見的做法是將各個變因以統計的型式表示，再使用蒙地卡羅(Monte Carlo)模擬來分析，若要得到較準確的統計結果，也需模擬數千筆以上的樣本(samples)，亦是相當耗時的過程。
在本論文中提出了一個快速尋找電路最差角落的方法，可以分析出幾個合適的角落進行模擬，而不必跑完所有角落，有效提升了角落分析的效率。該分析的結果也可以用來篩選蒙地卡羅模擬的樣本，只有可能性較高的樣本才會真正進行電路模擬，大大節省了蒙地卡羅分析的模擬時間。從幾個不同電路的實驗結果中可以看出，本論文所提出的方法確實都可以用少量的樣本模擬找到電路效能最糟的情況，大大提升了製程變異分析的效率以及準確度。 | zh_TW |
| dc.description.abstract | As the technology goes to nanometer scale, process variations in manufacturing become more and more significant. Those variations can be roughly classified as global variation and local variation. If the process variation changes circuit performance too much, it may cause the design fail to meet its specifications and decease the design yield. In order to guarantee the chip quality, analyzing global/local variations before manufacturing is essential.
For global variations, process-voltage-temperature (PVT) corners that combine the extreme cases of those factors are widely used to check the performance bound. However, in the advanced technology node, the number of PVT corners is growing exponentially. Exhaustive simulation of PVT corners is not practical for now. For local variations, Monte Carlo simulation is often used to handle the huge variable numbers by using the statistical model of each variable. However, accurate statistical results often require thousands of samples, which is also a time-consuming process to run thousands of circuit simulations.
This thesis proposes an efficient algorithm to find the worst-case corner of circuits. Instead of full corner simulation, only a few relevant corners are extracted to run circuit simulation, which greatly improves the efficiency of corner analysis. In addition, the proposed analysis can also help to choose the samples with higher possibility to be worst case in Monte Carlo simulations. Significant speedup can be obtained for Monte Carlo simulations because only a few samples are required to be simulated. According to the experimental results on several circuits, the proposed approach finds the worst cases in all circuits with very few samples, which greatly improves the efficiency and accuracy of process variation analysis. | en_US |
| DC.subject | 找尋最差效能 | zh_TW |
| DC.subject | 角落分析 | zh_TW |
| DC.subject | Worst Case Identification | en_US |
| DC.subject | PVT Corner Analysis | en_US |
| DC.title | 有效尋找角落分析與蒙地卡羅模擬之最差情形的方法 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Efficient Worst Case Identification Method for PVT Corner Analysis and Monte Carlo Simulation | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |