| dc.description.abstract | Dynamic random access memory (DRAM) is one key component in electronic systems. Recently,
multi-channel DRAMs have been proposed for three dimensional (3D) or 2.5D chips. Due to the
poor test accessibility, built-in self-test (BIST) method is considered a good approach for the postbond
testing of multi-channel DRAMs in 2.5D/3D chips. Various BIST schemes were presented to
test DRAMs. To support different test algorithms, most of those BISTs are designed as they have
the programmability of test algorithms.
In this thesis, we first survey existing programmable BIST schemes for RAMs. Comparison
of different programmable BISTs is conducted . Then, a hybrid BIST scheme for DRAMs is proposed.
The hybrid BIST consists of a microcode-based controller for supporting the metal-change
programmability of test algorithms and an FSM-based controller for supporting the in-field programmability
of mode registers and configuration parameters. Thus, if the needed test algorithms
are out of the test algorithms stored in the read-only-memory, only metal changing is needed to
change the supported test algorithms. The in-field programmability can meet the requirement of
post-bond test on the uncertainties of test thermal, number of stacked dies, driving strength of
drivers, and so on. We also have implemented the hybrid BIST for a multi-channel DRAM. Simulation
results show that only about 18.2K gates are needed to support March and non-March test
algorithms for a single channel within a 20Gb 4-channel DRAM using TSMC 90nm standard cell
library. Finally, a memory BIST compiler for DRAMs is proposed. The memory BIST compiler
can generate different types of memory BISTs including the FSM-based, microcode-based,
microcode programmable, and proposed hybrid BISTs. | en_US |