| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系 | zh_TW |
| DC.creator | 蘇文軍 | zh_TW |
| DC.creator | Wen-jun Su | en_US |
| dc.date.accessioned | 2015-1-16T07:39:07Z | |
| dc.date.available | 2015-1-16T07:39:07Z | |
| dc.date.issued | 2015 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=101523003 | |
| dc.contributor.department | 通訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | IEEE 802.16，是由電機電子工程師學會（IEEE）所通過的無線寬頻標準。現行的標準為IEEE 802.16-2009。現行的WiMAX技術即是基於此項標準而實作。IEEE 802.16規格中使用Turbo Product Code (TPC)碼作為其中一種通道編碼，提供了很好的錯誤更正能力。
TPC(Turbo Product Code)是一種利用兩個短長度區塊碼(Block Codes)以特定串接(concatenated)方式產生一長度較長之區塊碼，其解碼技術主要倚賴一soft-input/soft-output之區塊碼解碼器，典型是使用Chase Algorithm，配合反覆解碼技術，達到低複雜度與高性能之解碼功能。如IEEE 802.16標準中所使用基於Extended Hamming Code或偶位元檢查碼(Even Parity Check)之2-D Block Turbo Code (BTC)。
本論文研究內容在於以FPGA硬體架構設計與實現IEEE 802.16 TPC規格之解碼器，硬體架構主要包含以下模組：測試樣本產生模組(Test Pattern Generator)、漢明解碼(Hamming Decoder)+最大可能性(Maximum Likelihood Detection)模組、軟式輸入輸出(Soft Input Soft Output) 解碼計算模組及Turbo解碼資訊更新機制模組。
| zh_TW |
| dc.description.abstract | IEEE 802.16 is a wireless broadband standard adopted by the Institute of Electrical and Electronics Engineers (IEEE). The current version is denoted as the IEEE 802.16-2009 standard which is also known by the WiMAX technology. In this standard, a specifications of Turbo Product Code (TPC) code is used as one of the channel coding technology which provides a good error correction capability.
The TPC specified in 802.16 is a 2-D block turbo code (BTC) generated by a concatenation of a Hamming code with or without additional parity bit. The decoding technology relies mainly on a soft-input/soft-output (SISO) decoder of the block code, which is typically implemented with Chase Algorithm for complexity reduction, and an iterative message passage (turbo-decoding) scheme to achieve high performance in terms of the error correction capability.
The research topic of this thesis is on the hardware architecture design and realization of the 802.16 TPC decoder with FPGA. The hardware architecture mainly consists of following modules: Test Pattern Generator module, Hamming Decoder + Maximum Likelihood Detection module, SISO Decoder Computer module and the Turbo Message Update module.
| en_US |
| DC.subject | TPC解碼 | zh_TW |
| DC.subject | Chase Alogrithm | zh_TW |
| DC.subject | 現場可程式化閘陣列 | zh_TW |
| DC.subject | TPC Decoder | en_US |
| DC.subject | Chase Alogrithm | en_US |
| DC.subject | FPGA | en_US |
| DC.title | 802.16TPC解碼器之FPGA設計與實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Implementation of 802.16 TPC Decoder with FPGA | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |