DC 欄位 值 語言 DC.contributor 電機工程學系 zh_TW DC.creator 孫世洋 zh_TW DC.creator Shi-Yang Sun en_US dc.date.accessioned 2016-7-25T07:39:07Z dc.date.available 2016-7-25T07:39:07Z dc.date.issued 2016 dc.identifier.uri http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=102521001 dc.contributor.department 電機工程學系 zh_TW DC.description 國立中央大學 zh_TW DC.description National Central University en_US dc.description.abstract 隨半導體產業發展與電腦相關產業的興起，資料傳輸頻寬逐漸上升，傳統並列傳輸方式漸漸被串列傳輸取代，例如DisplayPort、SATA、USB、及PCI-E 等皆使用串列傳輸介面。本論文參考USB 3.1 Gen1規格實現一個具自適應等化器之資料與時脈回復電路。 本論文將自適應等化器控制機制內嵌於資料與時脈回復電的相位偵測器中，使得原本兩個獨立的迴路能夠結合在一起，以達到降低硬體複雜度，與此同時，利用混合式半速率二進位相位偵測器與電流模式電容放大技術來達到低的功率消耗與降低面積。本論文使用TSMC 90 nm (TN90GUTM) 1P9M之製程來實現，電路操作電壓為1 V，輸入資料速率為5 Gbps時，回復時脈速率為2.5 GHz，峰對峰值抖動量15.56 ps，均方根值抖動量為2.27 ps，在通道長度為0-m時(短通道)，等化後資料的峰對峰值抖動量為21.33 ps，方均根值抖動量為3.41 ps，在通道長度為1.5-m時(長通道) ，等化後資料的峰對峰值抖動量為24 ps，方均根值抖動量為4.84 ps。功率消耗為21.9 mW，其中資料與時脈回復電路之功率消耗為15.1 mW，自適應等化器之功率消耗為6.8 mW，晶片面積為1.38 mm2，核心電路面積為0.13 mm2。 zh_TW dc.description.abstract In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, and PCI-E. This study presents a clock and data recovery (CDR), and takes USB 3.1 Gen1 specification as reference material. In this thesis, the control loop of adaptive equalizer is embedded in phase detector of clock and data recovery to achieve low hardware complexity, meanwhile, using hybrid phase detector and current mode capacitance magnification method achieve small area and low power. This proposed was implemented by TSMC 90 nm (TN90GUTM) 1P9M process with 1V supply voltage. When CDR operates at 5 Gbps, the frequency of recovered clock is 2.5 GHz, peak-to-peak jitter of recovered clock is 15.56 ps, RMS jitter of recovered clock is 2.27 ps. When channel length is 0-m (short channel), peak-to-peak jitter of equalized data is 21.33 ps, RMS jitter of equalized data is 3.41 ps. When channel length is 1.5-m (long channel), peak-to-peak jitter of equalized data is 24 ps, RMS jitter of equalized data is 4.84 ps. The total power consumption of this work is 21.9 mW, the power consumption of CDR and adaptive equalizer are 15.1 mW and 6.8 mW. The chip area is 1.38 mm2 and the core area is 0.13 mm2. en_US DC.subject 資料與時脈回復電路 zh_TW DC.subject 鎖相迴路 zh_TW DC.subject 自適應等化器 zh_TW DC.subject Clock and Data Recovery (CDR) en_US DC.subject Phase Locked Loop (PLL) en_US DC.subject Adaptive Equalizer (EQ) en_US DC.title 以符碼間干擾偵測技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路 zh_TW dc.language.iso zh-TW zh-TW DC.title A 5 Gbps Half-Rate Clock and Data Recovery with Adaptive Equalizer Using ISI Detecting Technique en_US DC.type 博碩士論文 zh_TW DC.type thesis en_US DC.publisher National Central University en_US