| dc.description.abstract |
Automated layout design on analog circuits can significantly reduce the high error rate of the design, the time complexity of the layout of the high cost of operation and tedious task and expensive design costs.Due to the mismatch sensitive parasitic capacitance effects, components, process variation and gradient effect will lead to the layout result can be a bad layout, also caused inaccuracies and lower product yield.Most of analog circuits such as analog-digital / digital-to-analog converters or filters, etc., and its performance is dependent on accurate capacitance ratio.For most of the requirements of the exact capacitance ratio of the capacitor in parallel using multiple satellites units substituted single and considering a large parasitic capacitance caused by winding, in order to reduce some of the effects of the mismatch.
This paper propose automatic placement algorithm for analog/digital capacitor device,it follow rule of common-centroid, making the array dispersion, symmetry, coincident
and compactness, we use diagram method to test linearity and integrate algorithm with metric intoa user tool, user can quickly input placement in tool and simulate the result and also do detail change make sure the accurate of capacitor ratio. | en_US |