|dc.description.abstract||Tunnel field effect transistors (TFETs) is based on band-to-band tunneling (BTBT) to generate the current, and subthreshold slope (S.S.) could be less than 60 mV/decade. Unlike traditional metal oxide semiconductor field effect transistors (MOSFETs), which is based on drift-diffusion carriers to generate the current, which S.S. would be limited by kT/q.
For a hetero-epitaxial structure p+-i-n+ GaAsSb/InGaAs material was used in this study. Sourse is a heavy doped p+-GaAsSb, which is > 5 × 1019 /cm3 carbon doped, 51% arsenic and 49% antimony. Drain is a heavy doped n+-InGaAs, which is > 1 × 1018 /cm3 silicon doped, 51% indium and 49% gallium. The channel is a 150 nm undoped i-InGaAs layer.
In this study, we use optical exposure and wet etching method to fabricate the micron size TFETs. First, investigating temperature-dependent current-voltage characteristics of TFETs, which is divided into three different transport mechanisms. First region is like Shockley–Read–Hall (SRH) generation–recombination current, second region is trap- assisted tunneling (TAT) and third region is band-to-band tunneling (BTBT). Scaling the Al2O3/HfO2 effective oxide thickness (EOT) from 2 nm to 1.5 nm improves the gate control capability to channel. Using rapid thermal annealing (RTA) method to replace the furnace post-deposition annealing (F-PDA) maintains great p+-i-n+ epitaxial behavior. Finially, using pulsed I-V measurement to reduce the impact of traps to TFETs. At room temperature, the characteristics of this device could obtain the maximum on current (Ion) from 3.56 μA/μm which is measured by directly current (DC) to 9.01 μA/μm, the highest on/off current ratio (Ion/Ioff) is from 2.72 × 102 to 1.75 × 103, the peak to valley current ratio (IP/IV) of negative differential resistance (NDR) is from < 1 to 1.6, and the minimum S.S. is from 298 mV/decade to 55 mV/decade which is beyond 60 mV/decade.