|dc.description.abstract||This thesis focus on the design and analysis of the high spurious-free dynamic range and low dc power broadband track-and-hold amplifier. The content consists of two distributed amplifiers and two track-and-hold amplifiers. The design goals of the proposed circuits are broadband, high linearity and low dc power consumption. The circuit design, analysis, simulation, and measurement are completely presented in this thesis, and the discussion and conclusion are also addressed for the future works.
Two distributed amplifiers (DAs) are introduced in Chapter 2. To enhance the bandwidth and gain, the DAs are designed sing active and passive loads in the WIN’s 0.15 and 0.25 μm enhancement/depletion-pseudomorphic high-electron mobility transistor (E/D-PHEMT) process, respectively, and some circuit analysis is presented to verify the design methodology. The dc bias and device size selection is addressed with ideal component for the preliminary circuit simulation. The full-wave EM simulator is also adopted to evaluate the layout design. For the experimental results, the small-signal S-parameters, output 1-dB compression point (P1dB) and third-order intercept point (IP3) are completely performed. The measured 3-dB bandwidth of the DA using resistive load is from DC to 63 GHz with an average small-signal gain of 12 dB, and the total DC power consumption is 112 mW. The measured 3-dB bandwidth of the DA using active load is from 4 to 35 GHz with an average small-signal gain of 11 dB, and the DC power consumption is 138 mW.
Two track-and-hold amplifier (THAs) are designed using TSMC 0.18 μm SiGe process in Chapter 3 and 4. The switch capacitor and the switch emitter follower are employed in the track-and-hold stages of the THAs in Chapter 3 and 4, respectively. The introduction and design principle of the THAs are first presented in Chapters. To further reduce the feedthrough during the hold mode, a differential cancellation technique is proposed for the track-and-hold stage designed using switch capacitor. Moreover, the modified Darlington pair is employed to enhance the gain and bandwidth of the THA, and the chip area is also reduced. The full-wave EM simulator is also adopted for the layout designs of the THAs. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THAs are both wider than 7 GHz with insertion gains of -7 and -1 dB, respectively. For the THA using switch capacitor with cancellation technique, the measured SFDR and total harmonic distortion (THD) are better than 10 dBc, -10 dBc, respectively, when the input power is -4 dBm. The total DC power consumption is 132 mW. For the THA using switch emitter follower and modified Darlington pair, the SFDR and THD are better than 35 dBc, -35 dBc, respectively, when the input power is -4 dBm. The total DC power consumption is 84.7 mW.||en_US|