| dc.description.abstract | In modern communication systems, a voltage-controlled oscillator (VCO) is an essential building block. Since the demand for high speed data transmission rate is increasing, we were driven to investigate millimeter-wave communication systems. This thesis focuses on the millimeter-wave oscillator and frequency-locked loop (FLL) using an injection-locked technique to achieve low dc power consumption and low phase noise. Analysis, design and measured results for K-band high-division, broadband regenerative injection-locked frequency divider (ILFD) in Chapter 2. Analysis and design of the FLL and the sub-harmonic injection-locked K-band VCO with FLL self-alignment are presented in Chapter 3 and 4, respectively. Finally, a V-band sub-harmonic injection-locked quadrature VCO (SILQVCO) using a transformer coupled (TC) topology are proposed in Chapter 5. All of the designs in this thesis are fabricated using TSMC 90 nm GUTM CMOS process.
Several frequency dividers and the injection-locked theory are introduced in Chapter 2. The locking range of divide-by-6 and divide-by-5 ILFDs is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectors and the amplitude of the injection signal. The proposed K-band divide-by-6 ILFD features a locking range of 7.1 GHz and a 31.2% fractional bandwidth. The dc power consumption is about 28.8 mW.
Analysis of the FLL, including the theoretical models, transfer functions and models using ADS (advance design system) software with system setup of each blocks in FLL are proposed in Chapter 3. We can efficiently analyze the opened-loop and closed-loop responses of the FLL system. Based on the FLL design methodology in Chapter 3, a sub-harmonic injection-locked oscillator with frequency-locked loop self-alignment (SILFLL) are presented in Chapter 4. A theoretical model of the SILFLL is proposed, and the calculated phase noise and jitter are presented for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 24 to 26.1 GHz, the locking range for each control voltages is about 100 MHz. The measured output power is higher than -17 dBm over the range. When the injection-locked output frequency is 25.3 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -114.3 dBc/Hz and 56.6 fs, respectively. The total dc power consumption is about 50.4 mW, and this work has the best FOM as compared with literatures.
In Chapter 5, we proposed a V-band wide locking range SILQVCO with low dc power consumption. By using a transformer coupled (TC) topology, the proposed TC-SILQVCO features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed SILQVCO without source degeneration, and the TC-SILQVCO can be operated in lower dc supply voltage as compared to the conventional SILQVCOs, 2) the dc bias of the injector can be properly designed for maximizing locking range, 3) the parasitic capacitance provided by the injector can be reduced due to the impedance transformation, and 4) the larger device size of the injector can be properly chosen enhancing the third harmonic. A theoretical model of the proposed TC-SILQVCO is also established and it has been carefully verified with the experimental results. The free-running oscillation frequency of the proposed TC-SILQVCO is from 56.6 to 59 GHz with a tuning range of 2.4 GHz. As the control voltage is 0.6 V and the input power is 4 dBm with one-third output frequency, the measured locking range is 1.2 GHz. When the injection-locked output frequency is 56.6 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz~40 MHz) are -126.8 dBc/Hz and 18 fs, respectively. The minimum quadrature phase error and amplitude error are 0.32° and 0.26 dB, respectively. The dc power consumption is 19.8 mW. The FOM and FOMT are -209 and -222, respectively. | en_US |