| dc.description.abstract | Digital Video Broadcasting - Satellite - Second Generation(DVB-S2) is a digital television broadcast standard that has been designed as a successor for the popular DVB-S system. In comparison with DVB-S, besides QPSK, DVB include enhanced modulation schemes up to 8PSK, 16APSK and 32APSK, which increase of available bitrate over the same satellite transponder bandwidth. Otherwise, it can reduce the phase offset and have a good performance in channel interference.
The reaserch topic of this thesis is on the hardware architecture design and realization of the DVB-S2 inner receiver with FPGA, Including Symbol Synchronization, Carrier Synchronization and Frame Synchronization, and Soft-Decision module which supplys Log likelihood Ratio (LLR) to outer receiver. The Symbol Synchronization uses interpolator to solve timing offset and do the sampling process. The Carrier Synchronization uses the ideal constellation of QPSK, 8PSK, 16APSK and 32APSK to caculate the phase and frequency offset of the input signal.The frame Synchronization uses the SOF(Start of Frame) which is known data to design a correlator, and caculate the beginning of frame. Then, we can catch the frame we need and avoid the ambiguous of phase. About the Soft-Decision, in this thesis I use the complex rotaion to caculate the distance of the boundary of Hard-decision I had caculate in accurate method, and use the distance as the LLR to simplify the caculate. | en_US |