| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系在職專班 | zh_TW |
| DC.creator | 蔡仁彰 | zh_TW |
| DC.creator | Jen-Chang Tsai | en_US |
| dc.date.accessioned | 2018-7-18T07:39:07Z | |
| dc.date.available | 2018-7-18T07:39:07Z | |
| dc.date.issued | 2018 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=102553011 | |
| dc.contributor.department | 通訊工程學系在職專班 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在積體電路設計公司的最後一道關卡為積體電路佈局，意即將電路圖透過佈局軟體編修至可交予晶圓代工的電路佈局圖。在開發電路佈局圖歷程中，會因涉及智慧財產權而僅先提供馬賽克化的電路佈局圖(又稱為黑盒子)给予客戶端，客戶端在無法解析黑盒子的情況下，將委託代工廠協助確認電路佈局圖裡每一層多晶矽層及金屬層都可以通過晶圓代工廠所規範的密度確認，經檢驗完成後，再將完整電路佈局圖交予客戶端。然則，黑盒子在製作過程中必需兼具是否損及原始資料以及無法還原之特性。因此，本論文提出一種可以將電路佈局圖馬賽克化的方法，使供應商可以將帶有密度資訊的電路佈局圖，直接交給客戶端整合並且驗證密度測試，但卻無法辨識電路佈局圖的圖樣，更無法透過還原工程，盜取機密。 | zh_TW |
| dc.description.abstract | Layout of integrated circuits (IC) is the final process in IC design house, by using IC layout editor tool to verify the design is complete and ready to send to semiconductor foundries. Because the layout process involves intellectual property rights, it is generally provided to the clients with a mosaic cellview (so-called black box); the clients might further provide the design to semiconductor foundries for detailed check due to their limited inspection abilities. The semiconductor foundries would confirm the poly silicon and metal on each layer meet certain criteria and regulation. Once the process is complete, the design house would provide the detailed layouts. However, the production of black box shall fulfill the characteristics of whether to damage the raw data and unable to recover.
Therefore, this dissertation offers a methodology of mosaic IC layouts, for suppliers to provide it to the clients with a certain amount of density information for inspection whilst not able to distinguish and recover the overall cellview to steal confidential data. | en_US |
| DC.subject | 佈局 | zh_TW |
| DC.subject | 密度 | zh_TW |
| DC.subject | 保密 | zh_TW |
| DC.title | 基於馬賽克特性之低失真實體電路佈局保密技術 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Low distortion layout secrecy based on character of mosaic | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |