| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 楊志嘉 | zh_TW |
| DC.creator | Chih-Chia Yang | en_US |
| dc.date.accessioned | 2017-6-1T07:39:07Z | |
| dc.date.available | 2017-6-1T07:39:07Z | |
| dc.date.issued | 2017 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=103521017 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著半導體製程的不斷進步，製程變動造成元件之間的參數變異和不匹配越來越嚴重，出現了許多難以控制的製程變動問題。在現今多數的類比數位電路中，像是類比數位轉換器等等，性能取決於準確的電容比值，但經過製程變異後，電容比值是否又與預期設想的一樣，如何達到準確的電容比值就成了一個很重要的議題。因此，如果想使電路產生預期的理想效能表現，就必須妥善的處理電路中的不匹配。
本論文模擬了對於電容元件各種不匹配的處理方法，從相關係數的角度出發，利用元件的空間相關特性，接著模擬了線性梯度效應、氧化層梯度效應、CMP效應和溫度的梯度效應，採用製程能力指標(Process Capability Index)評估電容擺放的好壞，可根據想抵制的效應進行更有效率的擺放，這樣就可以達到較完美的抗系統變異電容陣列，最後將系統變異和隨機變異都考量之後，可模擬出更接近真實的效應，藉由製程能力指標去評斷排列是否有符合使用者需求。 | zh_TW |
| dc.description.abstract |
As the evolution of semiconductor process technology, the process variation will be more and more serious in device mismatch and parameter variation of components. The performance of many types of analog circuits, like ADC, filter, etc., relies on the implementation of accurate capacitor array ratios. But after the process variation, the capacitance ratio is the same as expected. How to achieve the exact capacitance ratio is a very important issues. Therefore, the approach of mismatch effects becomes a critical issue for better anticipated performance.
In this thesis simulated a method for improving mismatch of elements. In this method, we estimate capacitance placement by spatial correlation. Then simulated linear gradient、oxide gradient、CMP effect and temperature gradient. From the point of view of the correlation coefficient, Process Capability Index to assess the performance of the capacitors array. According to effect users want opposition to make effective placement, it will arrive to perfect capacitor array prevent of systematic variation. Finally, consider the systematic mismatch and random mismatch, we could get truly approaching effect, Through the process capability indicators to determine whether the placement has to meet the needs of users. | en_US |
| DC.subject | 電容陣列區塊 | zh_TW |
| DC.subject | 系統性不匹配 | zh_TW |
| DC.subject | 綜合能力指標 | zh_TW |
| DC.subject | Capacitance Array Block Placement | en_US |
| DC.subject | Systematic mismatch | en_US |
| DC.subject | Process Capability Index | en_US |
| DC.title | 陣列區塊排列之比率不匹配的性能指標 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A Performance Metric of Ratio Mismatch for Array Block Placement | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |