| dc.description.abstract | As transistors are scaled-down in the semiconductor industry, it is important to replace MOSFETs for low power application due to the ability to make device work with a lower supply voltage, without increase in OFF state currents. Unlike the MOSFET which uses thermal carrier injection, the TFET utilizes band-to-band tunneling as a source carrier injection mechanism. Advantages of TFETs include excellent switching characteristics, small operating voltage and low power consumption. Since the TFET has a different source carrier injection mechanism than does the MOSFET, it can achieve sub-60-mV/dec subthreshold slope. III-V material based devices with high ON current have been considered. The high tunneling probability due to the narrow and direct bandgap. Therefore, III-V material based TFETs are studied in this thesis.
There are three different epitaxy structures used in this study, one homo-junction structure and two different hetero-junction structures. In order to achieve the tunneling operation of n-type TFET, a heavily doped In0.53Ga0.47As is dedicated for source, n+- In0.53Ga0.47As is for drain, and undoped In0.53Ga0.47As is for channel in In0.53Ga0.47As homo-junction structure. The first hetero-junction TFET has a p+ GaAs0.51Sb0.49 source with an intrinsic In0.53Ga0.47As channel and a n+ In0.53Ga0.47As drain. The second hetero-junction TFET is similar to the hetero-junction TFET, with the exception that a 6-nm In0.7Ga0.3As “pocket” is grown next to the source to provide a smaller tunneling barrier.
In this study, we use optical lithography and wet etching method to fabricate the micron dimension TFETs. Different epi structures involve in on-stated current were studied for insulators including Al2O3/HfO2 (EOT of 2 nm) by ALD. At room temperature, the characteristics of the hetero-junction TFET with pocket could obtain the maximum on current (Ion) 11.98 μA/μm. | en_US |