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In radio frequency (RF) transceiver circuit, local oscillator (LO) is an indispensable building block, since the demand for high data transmission rate is increasing, Design a high-frequency, low power, low phase noise and low jitters LO is an important issue.LO with quadrature outputs in RF transceiver is for the applications of image rejection and modulation/demodulation. This thesis focuses on K-band LO with quadrature outputs to achieve low power consumption, low phase noise and low jitters. Analysis, design and measured results for K-band quadrature voltage-controlled oscillator (QVCO) using self-injection coupled (SIC) topology are proposed in Chapter 2. Analysis and design of the K-band sub-harmonic injection-locked QVCO (SILQVCO) using transformer coupled (TC) topology are proposed in Chapter 3. Analysis, design and measured results for a K-band TC-SILQVCO with frequency-locked loop (FLL) self-alignment are proposed in Chapter 5. All of the designs in this thesis are fabricated using TSMC 90 nm GUTM CMOS process.
Several topologies of QVCO are introduced in Chapter 2. The SIC-coupled, current reused and transformer feedback are investigated to obtain the design methodology. Also, the bit-controller is used to increase tunning range. The proposed K-band SIC-QVCO features a tunning range of 3.3 GHz and a 16.7% fractional bandwidth, the measured phase noise at 1 MHz offset is -109 dBc/Hz. The minimum quadrature phase and amplitude error are 0.28° and 0.13 dB respectively, and the DC power consumption is 8.4 mW.
Several frequency multiplier and the injection-locked theory are introduced in Chapter 3. The transformer coupled approach is adopted in VCO design, and the proposed VCO using self-injection coupled technique can generate quadrature signal. TC-SILQVCO using current reused technique can be operated in lower DC power consumption. The measured locked range of the K-band TC-SILQVCO is from 22.9 to 25 GHz and locking range for each control voltage is about 200 MHz. The measured output power is higher than -10 dBm over the range. The measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -120.7 dBc/Hz and 37.1 fs, respectively. The minimum quadrature phase error and amplitude error are 0.02° and 0.35 dB, the total power consumption is 7.2 mW.
In Chapter 5, we proposed a K-band TC-SILQVCO with frequency-locked loop (FLL) self-alignment. First, analysis of the FLL, including the theoretical models, transfer functions and models using ADS (advance design system) software with system setup of each blocks in FLL. A theoretical model of the SILFLL is proposed, and the calculated phase noise and jitter are presented for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 22.9 to 25 GHz, and the locking range for each control voltages is about 200 MHz. The measured output power is higher than -10 dBm over the range. The measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -119.4 dBc/Hz and 36.7 fs, respectively. The total DC power consumption is about 40 mW, and this work has the best FOM as compared with literatures. | en_US |