| dc.description.abstract | In this work, we continue the efforts of our lab on the development of a ferroelectric-based integrated passive device (IPD) process. We improve the fabrication process for the ferroelectric varactors with through substrate vias (TSVs) on silicon and also develop the fabrication process for chromium silicide thin-film resistors.
The advantages of ferroelectric varactors that adopt parallel-plate structure include high capacitance density, high tunability, and low bias voltage. However, their quality factors are limited by the thin bottom electrodes. We previously developed ferroelectric varactors with TSVs on high-resistivity silicon. The approach is to expose the bottom electrodes of the ferroelectric varactors by etching silicon substrate from backside and then thicken the bottom electrodes by gold electroplating. However, the measured quality factor is not as high as expected and the yield of the process is low. One of the reasons that result in the low quality factor is that the high-resistivity silicon substrate does not exhibit the expected high-resistivity property. Consequently, the microwave loss caused by the GSG (ground-signal-ground) pad becomes unexpectedly high. As for the low yield, the major reason is the poor uniformity of the backside vias.
From previous literatures, it is known that there is a mobile electron layer beneath the native oxide of a high-resistivity silicon substrate, causing that the resistivity is not as high as expected in practice. It is also known that, by bombarding the substrate surface with argon ions, the silicon surface would become amorphous. As a result, the mobile electron layer would not be formed and therefore the microwave loss of the GSG pad is reduced. By adopting the technique of dosing argon, we increase the resistivity of the silicon substrate from 45 Ω-cm to 150 Ω-cm.
As for the improvement of the fabrication process for the backside vias, our original recipe for silicon etching only contains one KMPR 1025 photoresist layer. Unfortunately, it is proven difficult to completely remove the photoresist. Because of the photoresist residue, the surface becomes quite rough. In this work, we spin on a layer of LOR 5A photoresist prior to the KMPR 1025. By doing so, we can completely strip off the photoresists, thereby reducing the surface roughness and improving the uniformity of the backside vias.
Finally, we also develop a fabrication process for chromium silicide thin-film resistors, which are commonly used for bias resistors in microwave circuits. The chromium silicide thin films are deposited using RF sputtering and the target used in the sputter is CrSi2. Measurement results show that the sheet resistance of 50-nm chromium silicide thin film is around 1–1.5 kΩ/□. From the measured data of the resistors with film thickness of 50 nm, 100 nm, and 200 nm, calculated that the resistivity of the chromium silicide thin film we deposit is around 4000–6000 μΩ-cm.
In this thesis, we successfully reduce the microwave loss caused by the GSG pads by dosing Ar in the high-resistivity silicon substrate. We also successfully improve the uniformity of the TSVs on silicon. Finally, we develop the process for fabricating chromium silicide resistors. Through these advances in the fabrication process, we make the ferroelectric IPD process developed by our lab more complete.
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