| dc.description.abstract | The concept of System-in-Package (SiP) is to integrate chips and components implemented by different process technologies into one package and form a system. Flip-chip bonding is an important SiP technology, which is used to connect the chip and carrier substrate with short flip-chip bumps. Compared with the conventional bond wires, flip-chip bumps possess lower parasitic inductance and are more adequate for high-frequency applications. In this work, on the carrier-substrate, benzocyclobutene (BCB) stacked via and electroplated gold flip-chip bump processes are developed. On the chip side, the technique of electroless nickel-gold plating on the chip pads is implemented. Finally, the chip is flip-chip bonded onto the carrier by gold-gold thermo-compressive bonding.
BCB is a dielectric material with low dielectric constant and high breakdown voltage, making it suitable for dielectric layers on flip-chip carrier substrates. To realize microstrip structure with BCB as the dielectric layer, we develop the BCB stacked via process. Spin-coating, exposure, developing, and curing of BCB are repeated three times to fabricate via holes on the three stacked BCB layers. Vias are successfully fabricated on the BCB dielectric layer, which has a total thickness of about 28 μm. The stacked via process is then used in the fabrication of microstrip lines with BCB as its dielectric and gold as its metal. The measurement results of the microstrip lines show that the insertion loss per unit length at 20 GHz is less than 0.15 dB/mm. By fitting the full-wave simulation results with the measurement results, it is found that the dielectric constant and loss tangent of the BCB are 2.65 and 0.002, respectively. Examining the measurement results, we find that the fabrication of some of the transmission line has failed. We believe that the failure is due to that the shape of the fabricated BCB vias is not uniform as its originally designed. In the future, the BCB vias can be fabricated using dry etching to obtain uniform via shapes and improve the yield.
On the implementation of flip-chip bonding, we connect chips that contain 50-Ω microstrip lines realized using TSMC 0.18-μm CMOS technology with coplanar waveguide (CPW) transmission lines on a sapphire carrier substrate by flip-chip bumps. We subsequently deposit nickel and gold on the aluminum pads of the CMOS chips by electroless plating. On the carrier substrate, the flip-chip bumps with about 12-μm height are fabricated using gold electroplating. The chips are then flip-chip bonded onto the carrier by gold-gold thermocompressive bonding. Measurement results show that, at 10 GHz, the return loss of the flip-chip bonded transmission line is still greater than 20 dB. By subtracting the losses of the microstrip on the chip and CPW lines on the carrier, it is calculated that the insertion loss contributed by flip-chip contact at single side is 0.04 dB at 10 GHz.
In this thesis, we develop an effective fabrication process for making stacked vias on BCB and successfully use the process to realize low-loss microstrip lines with BCB as the dielectric layer. In addition, we implement an electroless plating process to deposit nickel/gold on pads of CMOS chips. We also develop an electroplating process to fabricate gold flip-chip bumps on sapphire carrier substrates. Finally, we demonstrate the gold-gold thermocompressive bonding to connect the chips and carrier substrates, realizing low-loss flip-chip contacts at microwave frequencies. In the future, we can combine these processes to fabricate SiP modules on carriers with BCB as the dielectric layer.
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