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For supporting an ever-increasing number of cellular handset users, RF transceivers for the 5th generation of wireless communication system need to deliver the demands of broad bandwidth and high data rates. Moreover, low cost, low power consumption, and high integration are also the proliferating requirements in wireless transceiver design for next generation mobile handsets. A mixer is one of the essential sub-circuits in receivers and transmitters to complement the frequency translation. This thesis based on mixer design can mainly contains five parts, namely the motivation, two wideband mixers for C/X band applications, a quadrature transmitter for 5 GHz, and the future work.
The first work in Chapter 2 is fabricated in tsmcTM 0.18 μm CMOS technology. The author applied a frequency doubler for sub-harmonic pumping technique whose local (LO) frequency is an half of the desired RF frequency. This proposed mixer is adopted passive architecture and driven by drain port, leading to improved performances in terms of power consumption, noise, linearity, and conversion loss. The experimental results are described as follow, a conversion loss of 6.7 dB, input 1-dB compression point of 1.5 dBm, an IIP2 of 39.5 dBm, an IIP3 of 11.9 dBm, and a double sideband (DSB) noise figure (NF) of 10.8 dB with 0 dBm LO drive power. Due to doubly balanced configuration, the proposed mixer achieved outstanding isolation performance of better than 30 dB. The 3-dB bandwidth is measured from 6 to 12 GHz and total dc power dissipation of 3.3 mW at 1.5-V supply. The die size is 0.87 × 0.93 mm2.
The second work in Chapter 3 is implemented in tsmcTM 0.18 μm CMOS technology. For the purpose of enhanced linearity and mitigated noise, the conventional Gilbert upconversion mixer is replaced by a passive current mode mixer. In addition, a differential pair of cascode power amplifier driver with RC feedback is presented following the passive mixer to provide medium output power in the transmitter chain. By using resonator coupling technique, the transformer is successfully demonstrated and realized the wideband power matching for the previous power amplifier driver to meet the optima output power. The proposed upconversion mixer exhibits the measured conversion gain of 6.24 dB, output 1-dB compression point of -0.18 dBm and OIP3 of 9.6 dBm under the LO power of 4 dBm. The LO-to-RF isolation is better than 22.5 dB within the desired 3-dB bandwidth from 5 to 12.4 GHz. The chip consumes the dc power of 79.8 mW and occupies 1.53 × 0.95 mm2.
In Chapter 4, a transmitter prototype incorporated with quadrature mixer, 25% duty-cycle LO generation, and power amplifier driver is designed and fabricated in standard 0.18 μm CMOS technology. To eliminate the side-band frequency without any integrated sideband-reject filters, a quadrature mixer, which mixes the in-phase (I) and quadrature (Q) input baseband frequency signals with in-phase and quadrature phase LO signals. The frequency divider of current mode logic is widely and practically applied to generate quadrature signals, LO_I+, LO_I-, LO_Q+, LO_Q-. Furthermore, a passive current mixer switching with 25% duty-cycle LO is presented, which improves 3 dB higher conversion gain, better NF, and the flicker noise less than that switching with 50% duty-cycle LO. The IQ transmitter demonstrates measured conversion gain of -4.67 dB, which is biased at 1.8-V and dissipates 128.4 mW. The measured LO suppression and sideband suppression are -25.1dBc and 5.17 dBc, respectively. All aforementioned measured results are under LO input power equal to 10 dBm. The die size is 1.61 × 1.16 mm2 and will be bonded to the printed-circuit board (PCB) for testing. | en_US |