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This thesis presents a fully integrated receiver (Rx) front end and low noise amplifiers (LNAs) in tsmcTM 90 nm and 180 nm CMOS technologies. The CMOS RX front end with wideband, low power and low noise is the most challenging circuit due to its low gm, high substrate loss, and low breakdown voltage. Therefore, the main goal of this thesis is to adopt transformer feedback technique to achieve high gm value of the transistor. Meanwhile, the adopted technique also improves the performance in noise figure (NF) and bandwidth. Two LNAs were designed by using gate-source transformer as the wideband matching network which increases the gm value at high frequency regime. The coupling equation of this transformer feedback was derived in this thesis. An inverter type LNA, which has higher gm than CS amplifier, was designed in I-path receiver to obtain a wideband and high integration receiver. The noise contributions of the passive mixer, TIA (Trans-Impedance Amplifier) and the RX front end operated in voltage or current mode are particularly considered to obtain wideband low noise performance. It has to be noted that RC shunt-shunt feedback TIA determines the channel bandwidth of the receiver. After then, the I-path RX front end were integrated into fully integrated I/Q RX front end which was designed by utilizing 25% LO duty cycle to solve the major concerns of the I/Q receiver, i.e., I/Q cross talk and image frequency problems.
The first implemented wideband LNA for C/X band was designed by using gate-source transformer feedback technique in tsmcTM 180 nm CMOS. The transformer feedback technique improves the linearity of the LNA. The measured peak gain and |S11| are 12.04 dB and below -10 dB from 4.5 GHz to 10.1 GHz, respectively. The measured noise figure (NF) and IIP3 are 3.04 dB and 2.5 dBm, respectively. The total power consumption is 9.71 mW.
The second LNA exhibits a wideband performance from 0.7 to 11.9 GHz which was designed an inverter type LNA with a gate-source transformer feedback in tsmcTM 180 nm CMOS. The gm value in the inverter type LNA can be peaked by gate-source transformer feedback topology. The measured peak gain and |S11| are 10.3 dB and below -10 dB from 0.8 GHz to 9.1 GHz, respectively. The measured NF and IIP3 are 4.3 dB and 0.3 dBm, respectively. The power consumption is 13.71 mW. The chip area including pad is 0.71 × 0.57 mm2.
The third design is a low power wideband receiver which integrates an LNA, a Balun, a passive mixer, and a TIA in tsmcTM 90 nm CMOS. These noise contributions of the passive mixer, TIA and the RX front end operated in voltage or current mode are particularly considered to obtain wideband low noise performance. The measured peak conversion gain and |S11| are 35.2 dB and below -10 dB from 3 GHz to 11.7 GHz, respectively. The measured NF and IIP3 are 2.47 dB and -22.5 dBm, respectively. The measured LO to RF isolation is below -78 dB. The total power consumption is only 24 mW. The core chip area is 1.124 × 0.56 mm2.
The fourth design is a low power wideband I/Q receiver which integrated an LNA, a Balun, a pair of I/Q passive mixers, a 25% duty cycle LO and a TIA in tsmcTM 90 nm CMOS. This fully integrated I/Q receiver also provides a three-level gain control by utilizing variable resistors that enhances the linearity performance. The measured peak conversion gain and |S11| are 27.2 dB and below -10 dB from 5 GHz to 10 GHz, respectively. The measured NF and IIP3 are 5.9 dB and -9 dBm, respectively. The measured LO to RF isolation is below -100 dB, The total power consumption is only 30.8 mW. The core chip area is 1.04 × 1 mm2. | en_US |