博碩士論文 104456025 完整後設資料紀錄

DC 欄位 語言
DC.contributor工業管理研究所在職專班zh_TW
DC.creator廖芸箴zh_TW
DC.creatorYun-Chen Liaoen_US
dc.date.accessioned2017-5-5T07:39:07Z
dc.date.available2017-5-5T07:39:07Z
dc.date.issued2017
dc.identifier.urihttp://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=104456025
dc.contributor.department工業管理研究所在職專班zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract隨著車用產品與隨身電子產品的蓬勃發展,顯示器產業的產值仍不斷成長。隨著中、日、韓等國競爭,面板產業競爭激烈,為增加市場競爭力,如何加快面板開發速度和良好的產品良率,成為各企業努力的首要目標。公司的製程良率不僅直接影響到產品品質,也影響著生產和報廢成本的高低,因此製程良率成為決定公司營運好壞的關鍵因素。 現今許多公司都使用六標準差手法追求產品之高品質,利用數據化的分析來推動問題並提供解決方法,有效分析造成問題的根本原因並加以改善。本論文以TFT-LCD產業Array製程為研究實驗,以六標準差手法進行專案管理的方式進行產品良率及製程參數最佳化之改善。首先使用特性要因圖找出產品主要影響良率的因素,再利用柏拉圖分析找出線不良的成因。後續利用分析手法,找出影響產品品質關鍵的重要因子:(1)Array製程中的成膜製程之Hillock不良(2)SDR製程停留時間過久。以DOE實驗設計方式進行多種參數組合之測試分析,將成膜製程參數中的成膜溫度和傳送溫度降至常溫,搭配SDR製程的停留時間控管在一天以內,並將參數最佳化導入量產品之生產。有效將個案公司之中小尺寸面板產品的線不良不良率由34%降低至3%,其改善的財務效益:報廢成本 = 800萬-20 萬 = 780萬。不僅有效提升中小尺寸產品良率,並可大幅降低開發成本,成功驗證此分析手法提升品質之水準。zh_TW
dc.description.abstractDisplay industry of output value is still growing,with the growth of automobile electronics and portable electronic products. With the display industry of competition in China, Japan and other countries,taiwan display industry in order to increase market competitiveness, how to accelerate product development speed and good product yield is most important.The display company′s of process yield is not only impact on product quality, but also impact on production costs,so process yield is a critical factor for company′s operating. Many apply six-sigma method to pursue high-quality product.Digitiz companties ation is mainly used to analyze the root cause and further improve the fundanmental problem.This thesis studies the Array process in TFT-LCD(Thin Film Transistor Liquid Crystal Dispaly)industry.The six-sigma project managemaent is applied to improve product yield rate and optimal parameter. First we applied Cause and effects chart to analyze the possible factor of defect rate.Moreover,Plato,instrumental analysis,‎ statistical method,DOE are applied to find out some major factors.Finally,the influence on Array process resulting in the main factors of source line defect are the two factors: deposit of film temperature and loadlock temperature in physical vapor deposition process,waiting time in source drain romove photoresist process. Based on design of experiment,multiple parameter combinations are tested and analyzed.The results show that deposit of film temperature and loadlock temperature keep room temperature and waiting time control on one day.When the optimal combination is appplied to mass production,the source line defective rate is decrease from 34% to 3%.Scrap cost is decrease from eight million to two hundred thousand.Furthermore,the process can also achieve more productive and efficient.The study reveals that the proposed method can successfully imporve the quality.en_US
DC.subject六標準差zh_TW
DC.subjectTFT-LCDzh_TW
DC.subjectArray製程zh_TW
DC.subjectHillock不良改善zh_TW
DC.subjectSix-sigmaen_US
DC.subjectTFT-LCDen_US
DC.subjectArray processen_US
DC.subjectHillock defecten_US
DC.title應用六標準差於TFT-LCD Array製程Hillock不良改善之研究-以A公司為例zh_TW
dc.language.isozh-TWzh-TW
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

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