| dc.description.abstract | Currently, the layouts of analog circuits are often generated manually. Although some EDA tools can help to reduce design efforts, the complexity of layout constraints is still a big issue that limits the development of EDA tools. In the literature, there are many works related to the placement of analog circuits. However, few of them are discussing about the placement of high-voltage circuits. Compared with general circuits, the design of high-voltage circuits is more complex with more constraints. Since high-voltage circuits demand higher operating voltages and wider voltage ranges, transistors often require isolation rings around them to protect transistors from disturbing each other. Because isolation rings will occupy large chip area, it is necessary to develop proper EDA tools for the placement optimization with isolation rings to reduce the chip cost. Due to the sensitivity of high-voltage circuits, some additional constraints such as symmetry and routability should be considered during placement stage, which further increases the difficulties of EDA tools.
This thesis proposes a placement flow to consider both symmetry constraints and isolation rings for the placement optimization of high-voltage circuits. First, we analyze the size and constraints of the P-cell elements in the original circuits. Following the extracted constraints, we will adjust the location of transistors inside every isolation rings to change the shape of isolation rings. Meanwhile, different shapes of isolation rings will be considered simultaneously during the placement algorithm to optimize the layout area. According to the experimental results, the proposed placement algorithm is able to reduce the chip area for high-voltage designs with isolation rings and still keeps the algorithm efficiency. | en_US |