| dc.description.abstract | Two novel level-shifter architectures based on cross-coupled latch pairs for high voltage level-shifter applications was proposed and analyzed in this thesis. Since high votlage power transistors were employed as isolated protection devcies inside the level shifters, and the delay caused by Miller effect exists while power transistors switch on and off, two different high voltage level shilfters with resisitive loading and zener diode in series with a resistor, respectively, were designed to increase the transtion speed of the level shifters. In addition, to understand the roles of DPW_NBL isolated ring of the high votlage process while different reverse bias votlage applied with and effects on the performance of the level shifters, the N+ deep burried layer in the low voltage region and the high voltage region, respectively, were applied with the same and different voltage levels, separately, to examine the effects. In order to verify the proposed architectures, three kinds of different high voltage level shifters, including level-shifting from low voltage to high voltage, and high voltage to low voltage, were designed using TSMC 0.25um 60V Bipolar-CMOS-DMOS (BCD) process. The performance matrix (Figure of merit) was built and analyzed. The designed 7 different level-shifter circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a 20 ~ 25V square wave occupy total area of 2603um x 611um, and the other 7 circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a -20 ~ -25V square wave occupy the area of 2595.7um x 649.4um, respectively. | en_US |