dc.description.abstract | The minimum-mean-square-error (MMSE) plays a significant role in the massive multiple-input-multiple-output (MIMO) system uplink signal detection. However, matrix inversion computing complexity of the MMSE algorithm increases largely when the number of users is high, and hardware implementation is difficult. This thesis proposes a reducing complexity, frugal hardware resource, parallel processing and pipelining architecture MMSE detector. The channel encoder and decoder are used to improve bit error rate by soft output value. Firstly, Preprocessing units (PU) are used to calculate Gram matrix and Matched Filter output of the algorithm. In the literature, the lower-triangular (or upper-triangular) systolic array are proposed, the benefit of this architecture is that the value of the Gram matrix don’t need to store and then output to next stage directly, but needs more processing element for computing. In addition, since gram matrix is symmetric, the value of the Gram matrix bottom right corner (or upper left corner) don’t need to be calculated, and then the computing complexity can be reduced. According to symmetric of the matrix, this thesis reduces the computation of gram matrix value which only need to compute lowest. Hence, we can save hardware resource highly. Secondly, Jacobi iteration is used to decode in the second stage because it could process in parallel instead of sequential processing signal to calculate the soft output value. Finally, this design is verified on SMIMS VeriEnterprise Xilinx FPGA, and the proposed design is implemented in 90 nm CMOS technology. The core area is 3.34 mm^2, maximum clock frequency is 327 MHz, and dynamic power consumption is 47.3 mW. | en_US |