| dc.description.abstract | Object matching and identification are the popular research in the field of computer vision. The methods are mainly based on feature matching. In many feature extraction algorithms, SIFT (Scale invariant feature transform) is considered to be one of the best algorithms. It maintains the robustness for image scaling, rotation, deformation, and light changes. However, it require complex calculations and large amounts of memory that makes it difficult to achieve real-time.
In order to achieve real-time operations and reduce memory requirements, we propose a new SIFT hardware architecture and improve the SIFT algorithm in this thesis. In the step of constructing Gaussian pyramids, the original cascade operations is substituted by parallel operations. Although it increase the amount of calculations, we can reduce the amount of temporary memory and increase the speed. For the first octave images, we adapt a smaller scale space to simulate the high spatial frequency instead of upsampling image. The step of keypoint localization is replaced by appropriate threshold to filter out the bad extremum. In addition, the overall algorithm is based on segment which can be greatly reduced the internal memory in the design. We verified the hardware architecture on FPGA (Xilinx Artix7) and implemented by TSMC90nm process. Experimental results show that for an image with a resolution of 1280x720, the operating frequency can reach 152 MHz, the processing speed can reach 35.6 frames/s, and the internal memory requirement is 237 Mbits. | en_US |