| dc.description.abstract | Content addressable memory (CAM) is one widely used component in network systems.
Recently, memristor-based CAMs have been proposed to cope with the power and area issues
of conventional CMOS-based CAMs. Among them, memristor-based CAM is considered as a
good candidate. However, existing memristor-based CAM cell structures are much different
from conventional CMOS-based CAM structures. Also, the fabrication process of memristor
device may induce new failure mechanisms. Therefore, effective fault modeling and testing
techniques for memristor-based CAMs are imperative.
In this thesis, we define comparison faults for 5T-2R memristor-based ternary CAMs
(mrTCAMs) by injecting the electrical defects of resistive open, short, transistor stuck-on,
transistor stuck-open, and bridge. Then, a March-like test, March-MCAM, is proposed to
cover the comparison faults of 5T-2R mrTCAMs. The March-MCAM requires 6N Write
operations and (14N+2B) Compare operations to cover 100% comparison faults of an N×B-
bit 5T-2R mrTCAM array where 14N represents 2 compare operaitons are executed 7 times.
However, different cell structures were proposed to realize mrTCAMs. It is time-consuming
to manually do the fault modeling and test algorithm design. Therefore, we also propose an
automation method for the fault modeling of CAMs. Finally, we propose a test algorithm
generation method for CAMs. The proposed method uses the Read-Compare Detection
Equivalence (RCDE) concept to reduce the test generation time. Analysis results show that
the proposed method can achieve about 2 times of generation time reduction in comparison
with the method without using RCDE concept. | en_US |