| dc.description.abstract | With the progress of semiconductor science and technology, the number of metal-oxide-semiconductor field-effect transistors (MOSFETs) in integrated circuits continuely increases over the last 50 years following Moore’s Law. The rapidly increasing power consumption associated with transistor density becomes one of the major bottlenecks in the development of future integrated circuits. An intuitive approach to this problem is to lower the operation voltage and threshold voltage simultaneously. Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing (S.S.) is limited to 60 mV/decade or higher at room temperature. Whereas, tunneling field-effect transistors (TFETs) is considered as a promising candidate device for low voltage and low power integrated circuits, which is based on band-to-band tunneling (BTBT) to generate current that can break through the limit of S.S. (60 mV/decade).
In III-V compound semiconductors, InGaAs/GaAsSb material system allows us to modulate band lineups by changing their compositions to form staggered type heterojunction TFETs. In this study, pTFETs based on this material system is investigated using Synopsys Sentaurus TCAD tool. The effects of band alignment, doping concentration, gate position and traps at III-V/oxide interface on the electrical properties of InGaAs/GaAsSb TFETs are systematically studied. Simulation results show that there is a strong correlation between tunneling barrier (Ebeff) with on/off-currents (ION and IOFF). Higher Ebeff leads to lower ION and IOFF, while the lower Ebeff results in higher ION and IOFF.
To reach high ION and low IOFF, In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer is proposed to reduce Ebeff from 0.63 eV to 0.38 eV at the source/channel junction, which leads to an ION current equal to 24 μA/μm at VDS = - 0.3 V，VGS = - 0.5 V, while IOFF remains at 4×10-11 μA/μm at VGS = 0 V, simultaneously. To improve the device performance further and increase the switching speed, a low IOFF of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET combination with a high ION of InAs/GaAs0.1Sb0.9 insertion layer is proposed. Based on this design, ION can be further enhanced to 86 μA/μm and the threshold voltage can be reduced to - 40 mV. The effects of strain introduced by lattice mismatch between GaAsSb and In0.53Ga0.47As on the device performance are also studied. A 2 % compressive strain makes ION increase to 28 μA/μm, which is equal to the ION of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer, and its IOFF also remains at 10-11 μA/μm. | en_US |