| dc.description.abstract |
In traditional metal oxide semiconductor field effect transistors (MOSFETs), subthreshold swing (S.S.) is limited by kT/q (60 mV/dec) because of drift-diffusion carriers in the channel. However, the band-to-band tunneling current in tunnel field effect transistors (TFETs) is able to improve S.S. to be less than 60 mV/decade at room temperature. Compared with the Silicon based TFETs, the on-state current in III-V materials based TFETs can be increased due to higher tunneling probability from narrow and direct band gaps. Further using hetero-structure in the source side can reduce effective tunneling barrier height to induce higher on-state current. However, carriers may easily tunnel through the source side junction and cause the high leakage current in the off-state and ambipolar conduction.
In this study, we propose GaAsSb/InGaAs hetero-junction TFET with a novel composite channel. A high bandgap GaAsSb material is inserted near drain side channel and formed a composite channel. The proposed TFETs can improve the problem of leakage current and maintain the high on-state currents, thus higher Ion/Ioff and better S.S. can be obtained. The basic structure of TFETs in this study is a p+-i-n+ GaAsSb/InGaAs/InGaAs epitaxial layers. Sourse material is a heavy doped p+-GaAsSb. Drain material is a heavy doped n+-InGaAs. The composite channel material is a combination of 120-nm GaAsSb and 30-nm InGaAs layer..
By Silvaco Atlas simulation, compared with traditional GaAsSb/InGaAs TFET, the novel composite channel TFET shows leakage current can be reduced by five orders of magnitude, and ambipolar conduction is reduced. In on-state bias, the composite channel TFET demonstrates the same high on-state currents compared to GaAsSb/InGaAs hetero-junction TFET due to the same tunneling junction at the source side though higher gate voltage is required to reduce the blocking effect from GaAsSb in the channel. Therefore, higher on/off current ratio (Ion/Ioff) is observed.
The epitaxial layers of all TFETs were grown by MBE. Device fabrication was started with drain metallization. After that dry etching then wet etching method was used to define and expose the channel region before gate dielectric deposition. The dry etching then wet etching method is to overcome the different etching rate for two different materials in the channel, which results in the channel control ability. At room temperature, the characteristics of composite channel TFET showed the minimum off current (Ioff) of 5.43 × 10-6 µA/µm, the highest on/off current ratio (Ion/Ioff) of 23.20, and the minimum S.S. of 190 mV/decade. Due to the composite channel design, off-state current is redcued. But the on-state current is not as high as the value of simulation. The main reason is the GaAsSb layer in the composite channel is not totally controlled by gate bias. Am improved dry etching technique is required to fabricate device in order to demonstrate the advantages of the proposed TFETs. | en_US |