dc.description.abstract | This thesis focus on the design and analysis of the low droop rate, high speed broadband track-and-hold amplifiers. The design goals of the proposed circuits are broadband, low droop rate and low dc power consumption. The circuit design, analysis, simulation, and measurement are completely presented in this thesis, and the discussion and conclusion are also addressed for the future works.
The introduction and design principle of the THA will be presented in Chapter 2. A differential cancellation technique is proposed for the track-and-hold stage to reduce the feedthrough during the hold mode. To avoid charge injection, the dummy transistors are adopted in the track-and-hold stage. At the end of the Chapter 2, undersampling technique will be discussed.
The proposed THA with clock buffer is frabricated using TSMC 40 nm CMOS general purpose process in Chapter 3.The common-gate amplifier is adopted to enhance the bandwidth of THA. Moreover, the common source topology is employed to enhance the gain and bandwidth of the THA. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THA is 41 GHz with small-signal gain of -4.8 dB. The best SFDR is 49 dBc. The total DC power consumption is 104.1 mW, and the droop rate is 0.35 mV/ps.The chip size is 0.8× 0.9 mm2.
The proposed THA is frabricated using TSMC 0.18 μm SiGe general purpose process in Chapter 4.The distributed amplifier is adopted to enhance the bandwidth of THA. The dc bias and device size selection is addressed with ideal component for the preliminary circuit simulation. Moreover, the Cascode topology is employed to enhance the gain and bandwidth of the THA. The Cascode topology can also improve the isolation during the hold mode. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THA is 17 GHz with small-signal gain of -4.8 dB. The best SFDR is 54.8 dBc. The total DC power consumption is 180 mW, and the droop rate is 0.4 mV/ps.The chip size is 1 × 1.3 mm2.
The proposed Master slave THA is frabricated using TSMC 0.18 μm SiGe general purpose process in Chapter 5. To improve the droop rate of the THA in Chpater 4, the THA is resimulated and combined as a master slave topology.The distributed amplifier is be changed to two stages, because three stages will cost a lot of size of the chip . The dc bias and device size selection is addressed with ideal component for the preliminary circuit simulation. Becauce of the dc level is too high for next stage, the cascode topology is changed to common source. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THA is 10 GHz with small-signal gain of -5 dB. The best SFDR is 38.2 dBc. The total DC power consumption is 134 mW, and the droop rate is 4 μV/ps.The chip size is 2.6 × 1.8 mm2. | en_US |