| dc.description.abstract | In this paper, we introduce the design of low noise amplifiers (LNA) and power amplifiers (PA). Including two w-band low noise amplifiers, and three ka-band power amplifiers. First, a w-band cascode three stages LNA using TSMC 40nm General Purpose CMOS process is presented, because the parallel capacitor varied greatly up to 60.8% by process varation. The interdigitated capacitor is used in the next version to prevent capacitance changing. The construction is changed from cascode three stages to common source (CS) six stages to improve the measurement results of current, which is three times than the simulation results. The six stages LNA exhibits 21.6 dB gain, 3 dB BW from 87 to 100.6 GHz, a minimum noise of 7 dB at 87 and 97 GHz, and a GBP of 163.5 GHz. The chip size of the six stages LNA is 0.56 mm2.
In chapter 3, a ka-band binary combine power using WIN 0.15 μm InGaAs procss is presented. The first stage series a RC in parallel to improce stability. The second stage combines 4 FETs by binary combine. The interdigitated capacitor is used in output matching to prevent the capacitance varation by its small capacitance. The stability check schematics are summarized, including stability K, inter stage stability, and non-linear stability. The PA exhibits 13.9 dB gain, the output power at 1 dB gain compression point is 17.7 dBm, and 24-dBm saturation output power. The chip size of the PA is 4.6 mm2.
Analysis, design and measured results for cascode PA in chapter 4. The gate bypass capacitor of common gate FET is introduced. Comparison of two types cascode PA layout is presented. The first cascode PA exhibits 4.5 dB gain, the output power at 1 dB gain compression point is 18 dBm, and 765 mW power comsumption. The second cascode PA exhibits 5.2 dB gain, the output power at 1 dB gain compression point is 19.3 dBm, and 740 mW power comsumption. | en_US |