dc.description.abstract | The use of active and passive millimeter-wave transceivers for detection is a trend. In recent years, semiconductor process technology has matured, and the development of millimeter-wave applications using Silicon processes has also seen new advances. This thesis focuses on the application of millimeter wave injection locking technology in frequency divider and frequency locked loop to achieve low power consumption and low phase noise.Analysis, design and measured results for W-band high-division-ratio divide-by-3 injection-locked frequency divider (ILFD) in Chapter 2. Analysis, design and measured results of a V-band divide-by-6 ILFD are proposed in Chapter 3. Finally, the sub-harmonic injection-locked VCO with FLL self-alignment (SILFLL) are presented in Chapter 4. The V-band divide-by-6 ILFD and SILFLL in this thesis are fabricated using TSMC 90 nm GUTM CMOS process. The W-band ILFD is fabricated using TSMC 40 nm CMOS process.
First, frequency dividers and the injection-locked theory are introduced in Chapter 2. Then, the locking range of divide-by-3 is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectors and the amplitude of the injection signal. Using inductor matching improves the locking range of divide-by-3. The proposed W-band divide-by-3 ILFD features a locking range of 10.1 GHz and a 10.2% fractional bandwidth. The power consumption is about 7.2 mW.
In Chapter 3, we proposed a V-band divide-by-6 ILFD with low power consumption. The locking range is proportional to the device size of the injectors and the amplitude of the injection signal like in Chapter 2. The free-running oscillation frequency of the proposed ILFD is about 9.5 GHz and phase noise is -67.3 dBc/Hz. The measured locking range is about 5.6 GHz from 54.5 to 60.1 GHz with an input power -5 dBm. When the input signal is 144 GHz, the measured input and output phase noises at 100 kHz offset are respectively -125 and -140 dBc/Hz. The phase noise difference between input and output is about 15 dB, and it agrees with the theoretical calculation (20log6). The core power consumption is about 5.6 mW.
A sub-harmonic injection-locked oscillator with frequency-locked loop self-alignment (SILFLL) are presented in Chapter 4. First, the theoretical models and transfer functions of FLL are introduced, then using ADS (advance design system) software with system setup analyses FLL. We can efficiently analyze the opened-loop and closed-loop responses of the FLL system. Furthermore, a theoretical model of the SILFLL is proposed, and used to calculate phase noise and jitter for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 33.4 to 35.2 GHz and locking range for each control voltage is about 50 MHz. The measured output power is higher than -7 dBm over the range. When the injection-locked output frequency is 33.9 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -108.9 dBc/Hz and 144 fs, respectively. The total power consumption is about 70.6 mW. | en_US |