| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林憲佳 | zh_TW |
| DC.creator | Hsien-Chia Lin | en_US |
| dc.date.accessioned | 2017-11-21T07:39:07Z | |
| dc.date.available | 2017-11-21T07:39:07Z | |
| dc.date.issued | 2017 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=104521086 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本文提出一種低成本、高效率的感測器系統。利用180-nm CMOS技術降低電晶體本身臨界電壓，以及利用SIP(System In Package)技術，將被動元件電阻、電容、電感等元件製作於高阻抗基板上，利用高阻抗基板GIPD(Glass Integrated Passive Device)製程特性，以及其低損耗金屬走線的優勢，將被動元件的損耗與其本身的品質因數大幅的提升，大幅提升感測器的敏感度與效率，也取代掉傳統SOC(System On Chip)技術的不足與缺陷。
本文感測器-能量獵取器可利用獵取0.75、0.9、1.8、2.18、2.4-GHz等五個頻段的能量，來提供輸出電壓，整體效率最高可達35%，且輸出電壓可達到13.5V。本文感測器-低功耗接收機利用SIP技術減少級數間的功率損耗，且透過低功耗的設計應用，使得整體電路功率消耗僅有μW等級，且輸出可產生2-MHz的解調變訊號。
本文提出一種低成本、低功耗、高效能THz通訊技術。利用40-nm CMOS技術實現200-GHz通訊技術，藉由100-GHz壓控震盪器產生訊號，且透過PLL(Phase Locked Loop)去進行鎖定機制，將訊號穩定於100-GHz，再將訊號輸出至後級緩衝器與電壓放大器，將訊號放大至一定大小後，再透過功率放大器大幅度的將輸出訊號提高，接著利用倍頻器的效果，將訊號由100-GHz轉為200-GHz去透過振幅調變器進行調變，最後將訊號透過高頻天線進行輸出。本文提出之THz通訊技術可經由調變器進行調變，調變速度可高達20-Gb/s，且輸出功率可高達-0.6dBm。 | zh_TW |
| dc.description.abstract | This thesis proposes a low-cost, high-efficiency sensor system. This design use TSMC 180-nm CMOS process because the low-Vth and use system in package technology. All of the passive device R,L,C are design on the high-substrate process GIPD(Glass Integrated Passive Device). Use the low-metal loss to provide quality factor of the passive devices, which provides higher sensitivity and efficiency. Also this process can improve the disadvantages of the tradition process SOC(System On Chip).
This thesis proposes sensor-energy harvester can provide voltage with five band 0.75、 0.9、1.8、2.18、2.4-GHz respectively, and the most efficiency can be 35% and the output voltage can be 13.5 V. This thesis proposes sensor-low power receiver uses SIP (System In Package) technology to reduce stage power consumption from the stag to stage, and the total power consumption only cost μW order cause the lower power design application, while the output can provide 2-MHz signal.
This thesis proposes a low power consumption, high efficiency THz communication applications. It can be use at 200-GHz communication application by 40-nm CMOS technology. Phase Locked Loop (PLL) makes the frequency and phase stable which from 100-GHz voltage control oscillator (VCO) generates at input signal. And supply to next stage-Buffer & Amplifier when the input signal be locked. When signal is grew up enough for power amplifier (PA) to use. Signal gets more higher output power by power amplifier. The high-power input signal will be raised up from 100-GHz to 200-GHz by the frequency Doubler (2X), and it can be modulate from ASK mod. Finally the output single will be control at 20-Gb/s digital data which at 200-GHz to the next stage high-gain antenna, and the total output power can be -0.6dBm. | en_US |
| DC.subject | 感測器 | zh_TW |
| DC.subject | 太赫茲 | zh_TW |
| DC.subject | 通訊 | zh_TW |
| DC.subject | 互補式金氧半 | zh_TW |
| DC.subject | 高頻電路 | zh_TW |
| DC.subject | Sensor | en_US |
| DC.subject | THz | en_US |
| DC.subject | Communication | en_US |
| DC.subject | CMOS | en_US |
| DC.subject | High-Frequency | en_US |
| DC.title | 應用於感測器與太赫茲通訊之互補式金氧半高頻電路設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | CMOS High-Frequency Circuit Design for Sensor and THz Communication Applications | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |