| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 張凱彥 | zh_TW |
| DC.creator | Kai-Yen Chang | en_US |
| dc.date.accessioned | 2017-7-11T07:39:07Z | |
| dc.date.available | 2017-7-11T07:39:07Z | |
| dc.date.issued | 2017 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=104521109 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文利用tsmcTM 0.18-µm、tsmcTM 90-nm與WIN 0.25-µm GaN製程設計三顆功率放大器，電路設計上選擇操作於C/X頻段與Ku頻段，首先模擬不同製程之電晶體特性，選出最佳之電晶體大小與操作電流密度，結合變壓器形成寬頻匹配，最後量測電路特性以驗證電路設計之結果。
第一顆使用0.18-m CMOS製程於C/X頻帶之寬頻功率放大器，此功率放大器為兩級電路，採用電晶體疊接架構，輸出端使用傳輸線型變壓器，輸入端與級間匹配使用磁耦合變壓器作寬頻匹配，3 dB頻寬為5.1-11.5 GHz，傳輸增益為25.23 dB，飽和輸出功率為24.34 dBm，1-dB 增益壓縮點輸出功率為20.64 dBm，晶片面積為1.78 (1.968 × 0.904) mm2。
第二顆為應用傳輸線型變壓器於C/X頻帶之90-nm CMOS寬頻功率放大器，此電路延續第一顆電路設計，電路為兩級功率放大器設計，輸出端及級間匹配採用傳統型變壓器，輸入端採用傳輸線型變壓器作匹配，3 dB頻寬為5.1-11.2 GHz，傳輸增益為29.1 dB，飽和輸出功率為22.02 dBm，1-dB 增益壓縮點輸出功率為19.64 dBm，晶片面積為1.32 (1.522 × 0.866) mm2。
第三顆為應用0.25-m GaN製程於Ku頻帶之寬頻功率放大器，電路設計採全積體化之兩級共源級電路架構，傳輸線型變壓器運用於輸入端及輸出端以提供寬頻功率匹配，其3 dB頻寬為13-18.2 GHz，傳輸增益為14.71 dB，飽和輸出功率為32.26 dBm，1-dB 增益壓縮點輸出功率為27.6 dBm，晶片面積為3.13 (2.16 × 1.448) mm2。 | zh_TW |
| dc.description.abstract |
The thesis developed three power amplifiers that were designed in tsmcTM 0.18-µm CMOS, tsmcTM 90-nm CMOS and WIN 0.25-µm GaN for both C/X-band and Ku-band operations. Firstly, the transistor characteristics of different processes were simulated to choose best transistor size and current density. The broadband matching performance was realized by using transformer and Guanella-type transmission-line transformers. Finally, the design concepts were verified by measuring various circuit performances, such as s parameters, output power, linearity and digital modulation characteristics.
The first power amplifier was fabricated in tsmcTM 0.18-µm CMOS technology for C/X-band operation. The two-stage power amplifier adopted cascade topology. The broadband performance was achieved by using transmission-line transformer for output matching and magnetic transformer for both input and inter-stage matching networks. The measurement results of the first PA shows a small signal gain of 25.23 dB, the saturated output power (Psat) and the maximum power added efficiency (PAEMAX) are 24.34 dBm and 28.2%, respectively. The performances of the output 1-dB gain compression point (OP1dB) of 20.64 dBm. The chip area is 1.78(1.968×0.904) mm2.
The second circuit was fabricated in tsmcTM 90-nm CMOS technology for C/X-band operation. The circuit design flow follows the previous PA design which uses both transmission-line transformer and magnetic transformers to achieve broadband and low lossmatching. The wideband PA exhibits a peak gain of 29.1 dB, and 3-dB bandwidths from 5.1-11.2 GHz. The measured saturation output power, OP1dB, and maximum PAE are 22.02 dBm, 19.64 dBm, and 23.92%, respectively. The chip size is 1.32 (1.522×0.866) mm2.
The third chip presents a Ku-band monolithic microwave integrated circuit (MMIC) power amplifier in WIN 0.25-µm GaN technology. The broadband performance was achieved by using transmission-line transformer for both input and output matching networks. The amplifier achieves a 3-dB bandwidth from 13 to 18.2 GHz with small signal gain of 14.71 dB. Continuous wave measurements demonstrate a maximum saturated output power of 32.26 dBm and OP1dB of 27.6 dBm, respectively. The chip size is 3.13 (2.16 × 1.448) mm2. | en_US |
| DC.subject | 功率放大器 | zh_TW |
| DC.subject | 傳輸線型變壓器 | zh_TW |
| DC.subject | power amplifier | en_US |
| DC.subject | transmission-line transformer | en_US |
| DC.title | 應用傳輸線型變壓器於C/X頻段之CMOS功率放大器與Ku頻段之GaN功率放大器之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | C/X-band CMOS Power Amplifiers and a Ku-band GaN Power Amplifier Using Transmission-Line Transformer Technique | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |