| DC 欄位 |
值 |
語言 |
| DC.contributor | 資訊工程學系 | zh_TW |
| DC.creator | 張瑞慶 | zh_TW |
| DC.creator | Jui-Ching Chang | en_US |
| dc.date.accessioned | 2018-3-5T07:39:07Z | |
| dc.date.available | 2018-3-5T07:39:07Z | |
| dc.date.issued | 2018 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=104522040 | |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 二值影像處理被運用在多種靜態及串流影像當中，如物件辨識、追蹤、除雜訊，為了適應各種領域不同應用，以及即時影像處理的需求，本研究提出一可重組二值影像處理器以及開發平台，具有高度靈活性與即時影像處理之優點，能夠透過程式控制改變影像處理流程，處理器使用pipeline架構設計，提供形態學與邏輯運算元以及連通元件標記演算法，可重組的特點包含影像大小、二值化門檻值、結構元素及二值影像處理流程。本研究透過合成於Stratix V FPGA平台來驗證硬體效能，其中有16顆運算核心，處理器頻率可達379.94MHz，一秒鐘能夠處理362張大小為＂1024×1024＂ 的影像，並整合基因演算法及簡易開發平台，讓應用系統可以快速的開發，實驗結果證明本系統達到即時二值影像處理，能因應未來各領域之需求。 | zh_TW |
| dc.description.abstract | Binary image processing has considerable applications in image and video processing such as object recognition, tracking, and denoising. To enable real-time image processing for various applications, we propose a reconfigurable binary image processor with a flexible development platform and real-time processing capabilities. The developed processor enables the modification of image processing procedures by reprogramming the employed hardware registers. The processor involves a pipeline architecture design which can perform morphological and binary operations and connected-component labeling. The reconfigurable features of the processor include the image size, image thresholding, structure element, and binary image processing procedure. For performance validation, the processor was implemented on a Stratix V field-programmable gate array, which can process approximately 362 frames per second and can conduct 16 operations with a 1024 × 1024 image at 379.94 MHz. Moreover, proposed platform with a genetic algorithm can be utilized for rapidly and conveniently developing the application system. The experimental results demonstrated that the processor is suitable for use in real-time applications of binary image processing. | en_US |
| DC.subject | 可重組 | zh_TW |
| DC.subject | 二值影像處理器 | zh_TW |
| DC.subject | 數學形態學 | zh_TW |
| DC.subject | 基因演算法 | zh_TW |
| DC.subject | Real time | zh_TW |
| DC.subject | Reconfigurable | en_US |
| DC.subject | Binary image processor | en_US |
| DC.subject | Mathematical morphology | en_US |
| DC.subject | Genetic algorithm | en_US |
| DC.subject | Real time | en_US |
| DC.title | 一個可重組二值影像處理器及其開發平台設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of A Reconfigurable Binary Image Processor and Its Development Platform | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |