| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳紫宜 | zh_TW |
| DC.creator | Zi-Yi Chen | en_US |
| dc.date.accessioned | 2019-8-22T07:39:07Z | |
| dc.date.available | 2019-8-22T07:39:07Z | |
| dc.date.issued | 2019 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=105521036 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 近年來，隨著電子消費性產品的蓬勃發展，資料傳遞頻寬日漸提升，然而晶片與晶片之間的通道頻寬並未隨之上升，因此資料通過傳輸通道會受到符碼間干擾的影響導致訊號完整度下降，因此等化器被廣泛應用於接收端以補償資料經過通道所導致的衰減。
本論文提出一高通濾波決策回授等化器(High-Pass Filter Decision Feedback Equalizer, HPF-DFE)，可以讓回授訊號更貼近後游標符碼間干擾，可以同時針對資料符碼間干擾及邊緣符碼間干擾進行消除，在決策回授等化器延遲時間不同時，眼寬較不會有惡化的情形，並且利用連續時間線性等化器(Continuous time linear equalizer, CTLE)以及一階高通濾波決策回授等化器的整合，以達到降低硬體複雜度與整體功率消耗的效果，與此同時，在不同的通道衰減中，自適應系統可以分別對於CTLE以及HPF-DFE的補償量進行最佳化，達到更大的使用彈性。
本論文使用TSMC 40 nm (TN40G) 1P9M CMOS 製程實現，電路操作電壓為0.9 V，輸入資料速率為10 Gb/s，輸入時脈頻率為5 GHz，通道衰減可用範圍為4 dB到12 dB，在通道衰減4 dB時，補償後之四階脈波振幅調變(PAM-4)資料的峰對峰值抖動量為68 ps，方均根抖動量為23 ps; 在通道衰減12 dB時，補償後之PAM-4資料的峰對峰值抖動量為88 ps，方均根抖動量為28 ps。在通道衰減12 dB時之整體功率消耗為9.45 mW，其中CTLE以及DFE之等化器功率消耗為5.08 mW，自適應機制電路之功率消耗為4.37 mW，晶片面積為1.13 mm2，其中核心電路面積為0.04 mm2。
| zh_TW |
| dc.description.abstract | With the rapid development of electronic consumer products, the bandwidth of data transmission has been increasing. However, the signal integrity of high speed data transmission is worse since the limiting bandwidth of channel. Therefore, the equalizer is widely used at receiver to compensate the attenuate signal.
The thesis presents an innovative decision feedback equalizer with high-pass filter compensation. Both the data inter-symbol-interference (ISI) and edge ISI can be eliminated simultaneously. Therefore, the eye width of data will not deteriorate seriously when the loop delay is different. In addition, the CTLE and 1-tap HPF-DFE are integrated to reduce the hardware complexity and overall power consumption. At the same time, in different channel attenuation, the adaptive system can optimize the compensation of CTLE and HPF-DFE respectively, achieving greater flexibility of use.
This work is designed by TSMC 40 nm (TN40G) 1P9M CMOS process. When the channel loss is 4 dB, the peak-to-peak jitter of equalized PAM-4 data is 68 ps and the root mean square (RMS) jitter is 23 ps. When channel loss is 12 dB, the peak-to-peak jitter of equalized PAM-4 data is 88 ps and the RMS jitter is 28 ps. The power consumption is 9.45 mW at a supply voltage of 0.9 V and the channel loss of 12 dB. The entire equalizer and the overall adaptative system utilize 5.08 mW and 4.37 mW of power, respectively. The chip area is 1.13 mm2 and the core area is 0.04 mm2.
| en_US |
| DC.subject | 等化器 | zh_TW |
| DC.subject | 自適應 | zh_TW |
| DC.subject | 連續時間線性等化器 | zh_TW |
| DC.subject | 決策回授等化器 | zh_TW |
| DC.subject | Equalizer | en_US |
| DC.subject | Adaptive | en_US |
| DC.subject | CTLE | en_US |
| DC.subject | DFE | en_US |
| DC.title | 具高通濾波補償之10 Gb/s全速率自適應 四階脈波振幅調變等化器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A 10 Gb/s Full-Rate Adaptive PAM-4 Equalizer with High-Pass Filter Compensation | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |