| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 李祥維 | zh_TW |
| DC.creator | Shiang-Wei Li | en_US |
| dc.date.accessioned | 2018-7-31T07:39:07Z | |
| dc.date.available | 2018-7-31T07:39:07Z | |
| dc.date.issued | 2018 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=105521041 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 雖著科技的進步，人類的平均壽命逐漸提升，也因此各種穿戴式生醫電子醫療儀器以及生醫電子輔具如雨後春筍般崛起，固本論文將以如何降低功耗，來達到方便攜帶與提升電磁續行長效之目的。
本論文主要由兩個題目所組成，透過無線藕荷充電技術，使用整流器達到AC-DC再透過線性穩壓器做DC-DC的降壓完成整體系統架構。
題目一
吾人於本文中就藕合無線供電之生醫系統部分，提出了一種取代傳統實現二極體電路方式的新架構，透過達成近乎理想的功率電晶體切換並具有傳統二極體阻止逆電流之特性，大幅提升獵能器電壓與功率轉換效能。本案中述及之應用於無間斷恆久無線近場供電生醫系統之金氧半導體獵能器已透過台灣積體電路的標準金氧半180奈米製程完成布局後之設計模擬驗證，其效能可達到VCE=92.35% PCE=89.18%，整體面積則為1.1894mm2，可望作為新型綠能電子之相關應用的一個重要技術利基。
題目二
吾人於本文中探究PMIC低功耗的生醫系統部分，提出了一種改良版本的線性穩壓器電路的架構，透過最小電流0.5uA的 Quiescent Current已達成低功耗高續航力且Capacitor Free將電路積體化達成SOC，已達成將電路運用在穿帶式生醫系統中。本晶片已透過標準金氧半90奈米製程完成布局後之設計模擬驗證，有三種操作模式，在Normal Mode情況下滿載可達到50mA/100mA;在Low Power Mode情況下輕載則是可達到100uA;在Deep Sleeping Mode下則可維持邏輯閘的正常運作，儘管在靜態電流達到0.5uA時扔可以提供輸出電壓從0.7V到1.2V在Deep Sleeping Mode的情況下，可望作為新型節能電子之相關應用的一個重要技術利基。 | zh_TW |
| dc.description.abstract | In the recent with the increment of average age of humans ,various bio-medical wearable devices have been launched to help humans getting chronic diseases confirm their health.Therefore, how to reduce the power consumption to achieve the portability as well as the long battery life-time requurements is the most important demands of this thesis.
This thesis consists of two big theme. To finish the whole system ,it makes rectifier to convert AC voltage to DC voltage and then use low-dropout regulator to convert DC voltage to DC voltage step down with wireless charging technology.
In the first part, designs in this thesis are fabricated in the TSMC 0.18um 1P6M CMOS process. This article focuses on the conversion efficiency in wireless transmission of electricity. Instead of the traditional diode, proposing a new structure of CMOS which is using the active diode including power CMOS and diode to prevent the reverse current. The simulation of the complete rectifier achieves VCE=92.35% PCE 89.18% The whole chip area is 1.1894 mm2, including PAD.
In the second part, desings in this thesis are fabricated in the 90nm 1P6M CMOS process. This IP is consisted of a bandgap and a CMOS low-dropout regulator for low-power system-on-chip applications. It operates in three modes: normal mode for full load 50mA/100mA operation, low power mode for light load 100uA ,and deep sleep mode to sustain logic level. Even equal quiescent current 0.5u it could provide VOUT voltage 0.7V~1.2V in the deep sleeping mode. | en_US |
| DC.subject | 感應耦合 | zh_TW |
| DC.subject | 獵能 | zh_TW |
| DC.subject | 低功耗 | zh_TW |
| DC.subject | 低電流 | zh_TW |
| DC.subject | Low-Dropout Regulator | zh_TW |
| DC.subject | 金氧半導體 | zh_TW |
| DC.title | 靴帶式整流器與低功率低壓降線性穩壓器功率電子設計與研發 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Power Electronics Design and Implementation of Bootstrapped Rectifier and Low-power Low-dropout Voltage Regulator | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |