| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 姚昌宏 | zh_TW |
| DC.creator | Chang-Hung Yao | en_US |
| dc.date.accessioned | 2019-1-3T07:39:07Z | |
| dc.date.available | 2019-1-3T07:39:07Z | |
| dc.date.issued | 2019 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=105521052 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文以IEEE Std 802.3bwTM-2015[1]的車用乙太網路傳輸之數位基頻接收機規範來開發專屬的解碼演算法，著重在通道等化器演算法、時序回復電路（Timing Recovery Circuit）和數位電路設計，由於有線車用乙太網路通道屬於擴散通道，因此在等化器架構上採用改良後較低複雜度的定值模數演算法（Constant Modulus Algorithm, CMA）[2]及決策導向（Decision Directed, DD）演算法[3]來計算其等效的通道效應，通道等化器包含前饋等化器（Feedforward Equalizer, FFE）及決策回授等化器（Decision Feedback Equalizer, DFE）[4]；前者用來消除對前符碼間的干擾，後者用來消除對後符碼間的干擾。在時序回復電路部分，則是採用穆勒與姆勒（Mueller and Müller）演算法[5]的相位檢測方法，特別的是加入了改良後的可適性消除等化器（Adaptive Canceler Equalizer, ACE）[6]，如此使得穆勒與姆勒演算法的相位檢測器獲得的通道資訊更接近理想通道響應Sinc Function。在數位電路實現上使用Verilog HDL來描述與模擬，並使用台灣積體電路的40奈米製程（TSMC-40nm）來模擬實現電路，以及在SMIMS VeriEnterprise Xilinx FPGA上驗證其電路設計。 | zh_TW |
| dc.description.abstract | This research develops a proprietary decoding algorithm based on IEEE Std 802.3bwTM-2015[1] specification for digital Ethernet receiver in automotive Ethernet transmission and focuses on equalizer algorithms, timing recovery circuits and digital circuit design. Because the automotive Ethernet channel is dispersion channel, the equalizer architecture uses a modified Constant Modulus Algorithm (CMA) [2] in forward equalizer which has lower complexity and a Decision Directed (DD) [3] algorithm in decision feedback equalizer[4] The forward equalizer is used for eliminating pre-cursor and decision feedback equalizer is used for eliminating post-cursor. In the part of timing recovery circuits, the Mueller and Müller algorithm [5] is employed to find timing phase. In addition, the adaptive canceler equalizer (ACE) [6]is adopted to make channel information approximate to sinc function and then benefit for the Mueller and Müller algorithm. At last, the digital circuits of proposed equalizer and timing recovery circuit are simulated through Verilog HDL, implemented in TSMC 40 nanometer process and verified on the SMIMS VeriEnterprise Xilinx FPGA. | en_US |
| DC.subject | 定值模數演算法 | zh_TW |
| DC.subject | 決策導向 | zh_TW |
| DC.subject | 決策回授等化器 | zh_TW |
| DC.subject | 可適性消除等化器 | zh_TW |
| DC.subject | 穆勒與姆勒演算法 | zh_TW |
| DC.subject | CMA | en_US |
| DC.subject | DD | en_US |
| DC.subject | DFE | en_US |
| DC.subject | ACE | en_US |
| DC.subject | Mueller and Müller algorithm | en_US |
| DC.title | 應用於IEEE Std 802.3bwTM-2015車用乙太網路接收機之等化器與時序回復電路設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of Equalizer and Timing Recovery Circuit for IEEE Std 802.3bwTM-2015 Automotive Ethernet Receiver | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |