| dc.description.abstract | Recent years have witnessed active research in the development of RF and millimeter wave wireless system. The switch is a critical component for various functions, such as radar, transmitter-receiver (Tx/Rx) duplexing in a time-division-duplexing (TDD) system. To obtain a high performance switch, the choice of the process is a very important factor. For example, high-speed electron mobility and high breakdown voltage are the advantages of Ⅲ-Ⅴ process, and it is suitable for marine radar and marine navigation. However, it is hard to integrate to single chip and its chip size is big. In contrast, CMOS process has the superiorities of low cost, and easy integration. But its major drawback is having low breakdown voltage. We need to choose the suitable process to approach the specifications of the circuit. To support the research plan of the laboratory, we use GaN、GaAs and the CMOS processes to implement X band and Ka band switches.
The first work in Chapter 2 is fabricated in WINTM 0.1 μm GaAs technology. The author shunts two-stage switch to improve the isolation, and series two transistors to enhance the power handling. The simulated insertion loss of the proposed X band SPST is less than 0.8 dB, the isolation is better than 25 dB, and the IP1dB is 33 dBm.
The second work in Chapter 3 is fabricated in WINTM 0.25 μm GaN technology. The author used the equivalent quarter wavelength transmission line to reduce the chip size. The simulated insertion loss of the proposed X band SPDT is less than 1.97 dB, the isolation is better than 37 dB, and the IP1dB at 10 GHz is 47 dBm.
The third work in Chapter 4 is fabricated in WINTM 0.1 μm GaAs technology. The author used the resonant capacitance technique to resonate out the parasitic inductor of the transmission line to improve the isolation, and used distributed inductor to resonate out the parasitic capacitor of the MOSFET to improve the insertion loss. The simulated insertion loss of the first proposed Ka band SPDT is less than 1.8 dB, the isolation is better than 30 dB, and the IP1dB at 39 GHz is 35 dBm. The insertion loss of the second Ka band SPDT is less than 1.7 dB, and the isolation is better than 30 dB, and the IP1dB at 39 GHz is 32 dBm.
The forth work in Chapter 5 is fabricated in tsmcTM 90 nm CMOS technology. The author used the transformer -coupled and negative bias to improve the insertion loss and isolation without trade off both specifications. The simulated insertion loss of the proposed Ka band SPDT is less than 1.9 dB, the isolation is better than 40 dB, and the IP1dB at 35 GHz is 25 dBm. | en_US |