博碩士論文 105521102 完整後設資料紀錄

DC 欄位 語言
DC.contributor電機工程學系zh_TW
DC.creator楊瀚森zh_TW
DC.creatorHan-Sen Yangen_US
dc.date.accessioned2019-8-19T07:39:07Z
dc.date.available2019-8-19T07:39:07Z
dc.date.issued2019
dc.identifier.urihttp://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=105521102
dc.contributor.department電機工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract第四章為具低功耗無除頻器頻率追蹤迴路自對準之K頻段次諧波注入鎖定四相位壓控振盪器,首先介紹理論模型及轉移函數,接著利用第三章提到的模擬方法,由ADS(advance design system)軟體進行模擬分析鎖頻迴路的穩定度與相位雜訊及抖動,利用變壓器耦合技術、電流再利用自我注入耦合技術分別能進一步提升四相位壓控振盪器鎖定範圍及直流功耗的特性,並將低功耗無除頻器鎖頻迴路結合K頻段式次諧波注入鎖定四相位壓控振盪器,可以達到8分之一的參考訊號注入。量測的鎖頻範圍為21.7到23.6 GHz,各個控制電壓的鎖定範圍約為150 MHz,輸出功率大於-5 dBm。距載波偏移1 MHz的相位雜訊為-125.2 dBc/Hz,抖動量積分範圍由1 kHz到40 MHz為32.4 fs,電路直流總功耗為24.4 mW,和過去文獻比較擁有最佳的優化指數(FOM)。 zh_TW
dc.description.abstractThis thesis focuses on the research of frequency synthesizers with different architectures, and the application of millimeter-wave injection-locked technique in the conventional phase-locked loops (PLL) and the combination of divider-less frequency tracking loop method to realize frequency-locked loops (FLL), and further realize a quadrature outputs LO with low dc power consumption, low circuit complexicity, low phase noise, and low jitter. en_US
DC.subject壓控振盪器zh_TW
DC.subject鎖相迴路zh_TW
DC.subject鎖頻迴路zh_TW
DC.subject低相位雜訊zh_TW
DC.subject注入鎖定zh_TW
DC.subject射頻積體電路zh_TW
DC.subjectvoltagecontrolled oscilla-tor (VCO)en_US
DC.subjectphase-locked loopen_US
DC.subjectfrequency-locked loopen_US
DC.subjectlow phase noiseen_US
DC.subjectinjection-lockeden_US
DC.subjectRFICen_US
DC.title微波及毫米波低相位雜訊鎖相迴路與無除 頻器次諧波注入鎖定四相位鎖頻迴路zh_TW
dc.language.isozh-TWzh-TW
DC.titleMicrowave and Millimeter wave Low Phase Noise Phase Locked Loop and Divider less Sub harmonically Injection locked Quadrature Frequency locked Loopen_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

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