| dc.description.abstract | Abstract
With the rapid growth of wireless communication, the development of
semiconductor processes and the demand for high-speed data transmission, numerous
systems have been widely used in the microwave and millimeter-wave (MMW) bands.
In wireless communication systems, high-performance switches are an important block
in the radio frequency (RF) front end. Chapter 1 is the introduction of the thesis.
Chapter 2 introduces several RF switches and the design principles for single-pole
single-throw (SPST) and single-pole double-throw (SPDT) switches with travelingwave, distributed-type and stacked-FETs architectures. The switches are implemented
using 0.15 μm and 0.1 μm GaAs processes provided by WIN Semiconductors. The
SPDT traveling-wave switch has a measured bandwidth from DC to 36.5 GHz, an
insertion loss of less than 3 dB, an insertion loss of 3.1 dB at a target frequency of 38
GHz, and an isolation of 39.34 dB. The stacked-FETs SPDT switch has a measured
bandwidth from 23 to 49 GHz with an insertion loss of less than 2 dB and an insertion
loss of 1.47 dB and an isolation of 15.25 dB at a target frequency of 39.3 GHz. The
measured insertion loss degrades 1 dB (P1dB) is higher than 20 dBm.
Chapter 3, a W-band phase-locked loop front-end is designed using the TSMC
40nm CMOS process, and the center frequency is 94 GHz. A sub-harmonically
injection-locked quadrature voltage-controlled oscillator (QVCO) is integrated with an
injection-locked divide-by-three frequency divider. The QVCO has a measured
bandwidth from 93.28 to 97.37 GHz with a tuning range of 4.1 GHz, an output power
of higher than -22.4 dBm, and a phase noise at 1-MHz offset of -80 dBc/Hz. In addition,
the measured output powers of the injection-locked frequency divider also presented in
this chapter. The total DC power consumption of the circuit is 43 mW.
Chapter 4, a Ka-band integration of a neutralized wideband power amplifier (PA)
and a sub-harmonically injection-locked phase-locked loop (SILPLL) is implemented
using the TSMC 90 nm CMOS process. The measured SILPLL locking range is from
32.78 to 34.85 GHz, the locking range of each control voltage is about 55 MHz, the
output power is higher than -11.62 dBm, and the minimum phase noise at 1-MHz offset
is -106.3 dBc/Hz. The root mean square (RMS) jitter integrated from 1 kHz to 40 MHz
is 179 fs. The integrated SILPLL and PA chip has a measured locking range from 32.8
to 34.8 GHz and an output power of higher than 1.73 dBm. The total DC power
consumption of the circuit is 68.15 mW.X
Finally, Chapter 5 summarizes the research results presented in this thesis, and the
future works: sub-circuit in the millimeter-wave front-end transceiver switch and high
frequency quadrature voltage-controlled oscillator in the direct conversion transceiver
system. The research direction will be integrated RF front-end circuits, and the future
results are expected to meet the practical application of the transceiver. | en_US |