| dc.description.abstract | Based on convolutional neural network(CNN), we introduce a recognition and monitoring system for distinguish fetal electrocardiogram(fECG) signals and maternal electrocardiogram(mECG) signals from pregnant abdominal ECG recording, so that non-invasive electrodes detection can also achieve high detection rate. First, the data pre-processing make the abdominal ECG waveform is partitioned into 250ms as a segment with 10ms overlap area. Marking each segment into four different labels. In order to reduce the noise effect of the ECG signals in time domain, short-time Fourier transform is convert the ECG signals into two-dimensional time-frequency feature map. Then, we removing the baseline wandering. In this thesis, CNN architecture consists of two convolutional layers, two pooling layers, and fully connected layer, the final output result are probability value of 4 classes. The convolutional layer contains the activation function, using sigmoid function. Before the output layer, the data are also converted into the probability through the softmax function. In back propagation, calculating the error of the loss function, and the partial derivative with learning rate to update the parameters. In addition to the fusion, four leads record can generate one final result. We use two set of different ECG signal to test, the detection rates of pregnant a02, and a05 are 98.62% and 98.51%, respectively. Compared with the conventional K-nearest neighbor algorithm and random forest, a higher detection accuracy is achieved. For hardware design, after doing the complexity evaluation and quantization, we decided the FFT architecture with doubling algorithm to reduce the number of multipliers and use 〖radix2〗^2. The CNN architecture is designed by memory based, the schedule of the convolutional layer and local buffer design decreases the number of memory accesses to 7.2%, and 3.3%, respectively. The two hardware of convolutional layers are shared. And make the size of LUT reduced from 2^14 to 2^11 to reduce the area. Finally, the overall hardware design verified by FPGA. | en_US |