| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系 | zh_TW |
| DC.creator | 洪維崧 | zh_TW |
| DC.creator | Wei-Song Hong | en_US |
| dc.date.accessioned | 2018-7-17T07:39:07Z | |
| dc.date.available | 2018-7-17T07:39:07Z | |
| dc.date.issued | 2018 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=105523002 | |
| dc.contributor.department | 通訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在LTE上行傳輸中，通道編碼的部分會使用到迴旋碼以及渦輪碼，而本論文則是根據3GPP TS 36.212 規格書通道編碼中渦輪碼的部分進行探討。本文分成兩個部分：首先對於解碼器所使用的演算法進行介紹。其中，解碼器所使用的最大事後機率(maximum a posterior，MAP)演算法對對於硬體來說複雜度過高，因此會使用次佳的Max-Log-MAP演算法，且通道環境使用可加性高斯白雜訊(Additive white Gaussian noise，AWGN)通道來模擬其效能，以及對於演算法中各部分運算來進行模擬並制定所需的定點數資源。第二部分則是根據模擬結果，並以規格書中發射端所使用的渦輪碼編碼器及資料碼塊大小規格為基礎，設計出相應的解碼器硬體架構，且盡可能減少其複雜度。最後將解碼器以平行串接的方式來提高吞吐量，實現於FPGA驗證版上，並觀察以硬體實現後的解碼效能。 | zh_TW |
| dc.description.abstract | In the LTE uplink, tail biting convolutional coding and trubo coding are used in the channel coding, this paper follow 3GPP TS 36.212 to design turbo code decoder. We separate this paper into two parts. In first part, the algorithm which is used in the decoder will be introduced. The maximum a posterior probability (MAP) algorithm is too complex for the hardware, so the Max-Log-MAP algorithm which is next only to MAP is used. We use AWGN(Additive white Gaussian noise) channel as the simulation environment, and follow the algorithm simulation to decide the fixed-point. The second part, we follow the result of simulation and the trubo code encoder which provided from 3GPP TS 36.212 to design the turbo code decoder. Then, we use the parallel architecture to improve the throughput and implement on the FPGA to verification. Finally, we observe the performance after implementation | en_US |
| DC.subject | LTE渦輪解碼器 | zh_TW |
| DC.subject | FPGA硬體實現 | zh_TW |
| DC.subject | MAP | zh_TW |
| DC.subject | BCJR | zh_TW |
| DC.subject | MAX-log MAP | zh_TW |
| DC.subject | LTE turbo decoder | en_US |
| DC.subject | FPGA Implementation | en_US |
| DC.subject | BCJR | en_US |
| DC.subject | MAP | en_US |
| DC.subject | MAX-log MAP | en_US |
| DC.title | LTE規格渦輪碼解碼器之FPGA設計與實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | FPGA Implementation of LTE Turbo code Decoder | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |